6 ms·

What if any other RISC-V systems are UEFI capable? Major boon to usability.

thebeardisred 3y ago
We're working on that across all horizontally integrated platforms (i.e. datacenter class systems). I'm working on making sure that the vertical integration platforms see the value (as opposed to a requirement on das uBoot).
snvzz 3y ago
This is why RISC-V put a lot of effort on the boot process, and put it early. Relevant specifications include but aren't limited to SBI[0], UEFI protocol[1] and the ongoing platform specification[2]. RISC-V is quite ready to take over the datacenter, workstation and laptop markets, while dodging the issues derived from bespoke everything which other architectures challenging x86 suffer from. 0. https://github.com/riscv-non-isa/riscv-sbi-doc/releases https://github.com/riscv-non-isa/riscv-sbi-doc/releases 1. https://github.com/riscv-non-isa/riscv-uefi/releases/ https://github.com/riscv-non-isa/riscv-uefi/releases/ 2. https://github.com/riscv/riscv-platform-specs https://github.com/riscv/riscv-platform-specs
- dmitrygr 3y ago
  > RISC-V is quite ready to take over the datacenter The only thing missing: fast power-efficient core designs. Eh, how hard could that be? Other than that one little thing, totally ready to take over the datacenter.
  - snvzz 3y ago
    >Eh, how hard could that be? Really hard. >Other than that one little thing Not a little thing at all, but it is being taken care of by competent architects, who have succeeded at making very competitive high performing micro-architectures in the past. We know about Ventana Veyron, TBA before end of year, and Tenstorrent's Ascalon, TBA 2024, led by Wei-han Lien, previously lead architect of Apple M1. Ascalon is 8-wide, but also has smaller siblings at lesser decoder width, to cover a range of uses. According to a recent presentation by Jim Keller, it is expected to be competitive with projected Zen5 (also TBA 2024) performance but using considerably less power. There's also strong teams at Rivos, MIPS and SiFive working on very high performance cores, but we know less about these efforts.
    - dmitrygr 3y ago
      Sorry, i forgot the "/s" I know it is hard, which is why i am skeptical. XYZ is "working on" fast cores is years to decades away from "Server with XYZ cores now available to buy from vendor ABC"
      - deleted 3y ago
        [deleted]
  - rektide 3y ago
    Personally I think the fast power efficient core is on of the most solved issues. PDKs and un-core stuff (PCIe & USB IP) is I think the main constraint keeping these chips from doing great already.
    - dmitrygr 3y ago
      And yet ALL the existing buyable RISC-V chips out there now perform worse than even a half-decade-old ARM chip per MHz and per mW
      - deleted 3y ago
        [deleted]
      - monocasa 3y ago
        They're very competitive when comparing in the same gate count/process niche. It just takes more time for more complex designs to be verified.

We're working on that across all horizontally integrated platforms (i.e. datacenter class systems). I'm working on making sure that the vertical integration platforms see the value (as opposed to a requirement on das uBoot).

snvzz 3y ago

This is why RISC-V put a lot of effort on the boot process, and put it early. Relevant specifications include but aren't limited to SBI[0], UEFI protocol[1] and the ongoing platform specification[2]. RISC-V is quite ready to take over the datacenter, workstation and laptop markets, while dodging the issues derived from bespoke everything which other architectures challenging x86 suffer from. 0. https://github.com/riscv-non-isa/riscv-sbi-doc/releases https://github.com/riscv-non-isa/riscv-sbi-doc/releases 1. https://github.com/riscv-non-isa/riscv-uefi/releases/ https://github.com/riscv-non-isa/riscv-uefi/releases/ 2. https://github.com/riscv/riscv-platform-specs https://github.com/riscv/riscv-platform-specs

dmitrygr 3y ago
> RISC-V is quite ready to take over the datacenter The only thing missing: fast power-efficient core designs. Eh, how hard could that be? Other than that one little thing, totally ready to take over the datacenter.
- snvzz 3y ago
  >Eh, how hard could that be? Really hard. >Other than that one little thing Not a little thing at all, but it is being taken care of by competent architects, who have succeeded at making very competitive high performing micro-architectures in the past. We know about Ventana Veyron, TBA before end of year, and Tenstorrent's Ascalon, TBA 2024, led by Wei-han Lien, previously lead architect of Apple M1. Ascalon is 8-wide, but also has smaller siblings at lesser decoder width, to cover a range of uses. According to a recent presentation by Jim Keller, it is expected to be competitive with projected Zen5 (also TBA 2024) performance but using considerably less power. There's also strong teams at Rivos, MIPS and SiFive working on very high performance cores, but we know less about these efforts.
  - dmitrygr 3y ago
    Sorry, i forgot the "/s" I know it is hard, which is why i am skeptical. XYZ is "working on" fast cores is years to decades away from "Server with XYZ cores now available to buy from vendor ABC"
    - deleted 3y ago
      [deleted]
- rektide 3y ago
  Personally I think the fast power efficient core is on of the most solved issues. PDKs and un-core stuff (PCIe & USB IP) is I think the main constraint keeping these chips from doing great already.
  - dmitrygr 3y ago
    And yet ALL the existing buyable RISC-V chips out there now perform worse than even a half-decade-old ARM chip per MHz and per mW
    - deleted 3y ago
      [deleted]
    - monocasa 3y ago
      They're very competitive when comparing in the same gate count/process niche. It just takes more time for more complex designs to be verified.