The interesting part of RISC vs CISC now isn't the complexity of the instructions or whether they're variable or fixed length. Both ARM and RISC-V has aspects t

The interesting part of RISC vs CISC now isn't the complexity of the instructions or whether they're variable or fixed length. Both ARM and RISC-V has aspects that could be considered CISC-like in that regard. The interesting difference is the memory model of the instructions. What kind of dependencies between instructions you have to keep track of when decoding them. If I understand correctly, that's the thing that makes it very hard to scale x86 wider, as talked about in another top comment in this thread. The decoder doesn't necessarily scale linearly with the width of the decoder. Since ARM and RISC-V hasn't traditionally competed in the very high end ultra-wide superscalar CPU space until recently, it's possible that we're not going to see x86 held back until more advanced ARM/RISC-V manages to scale to a wider architecture than what x86 is reasonably capable of.