3 ms·
> To my surprise, ARM has an add-multiply instruction Fused multiply-add is (https://en.m.wikipedia.org/wiki/Multiply%E2%80%93accumulate_operation#Fused_multip
by Someone 3y ago
> To my surprise, ARM has an add-multiply instruction
Fused multiply-add is (https://en.m.wikipedia.org/wiki/Multiply%E2%80%93accumulate_operation#Fused_multiply%E2%80%93add https://en.m.wikipedia.org/wiki/Multiply%E2%80%93accumulate_...) is extremely useful and part of IEEE754-2008.
Because of that, it would surprise me if a modern CPU with floating point wouldn’t have it.
> And RISC-V uses 6 bytes because of shortened instruction for addition
That Wikipedia page claims RISC-V has fused multiply-add, so that may be compiler inefficiency. An answer to https://stackoverflow.com/questions/57248403/why-fused-multiply-add-operation-is-not-used https://stackoverflow.com/questions/57248403/why-fused-multi... says gcc can generate it at -O3)
- Findecanor 3y agoI think the parent poster might have been referring to the integer multiply-add instruction. In fact, 64-bit ARM does not have a regular MUL instruction. "MUL" is an alias to MADD with the zero register as addend. BTW. There is also no REM instruction. Flipping one parameter bit in the instruction word of an MADD makes the unit negate the product, changing it into a MSUB. That instruction is intended for computing the remainder after a DIV. So, when you need only a remainder there are eight instruction bytes — and high latency on small cores. Bigger ARM cores (such as Apple M1) perform macro-op fusion of DIV and MSUB to deliver both quotient and remainder in one operation.