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Apple's 'M3 Pro' chipset could feature 12 CPU cores
- ggm 3y agoApple has gone with an even split between high-performance and efficiency cores on the new silicon. He says the chip was spotted configured with 36GB of RAM. For context, the M2 Pro starts with 16GB of memory, and you can upgrade it to feature up to 32GB of RAM. Ugh. the "chip" has significantly less L1 and L2 cache. The device can be configured with 36GB of RAM. And, its 50% more cores than the M1 but only 20% more cores than the M2. Its the M3. Why quote its core-count on the M1 model, not the immediate past model? its a 20% corecount jump, smaller nm so probably better battery life all things being equal, and you can get 4GB more memory than the prior maxiumum which frankly seems a small jump: are they minning the parts, to avoid spend they have modelled isn't needed? Everyone I know maxes memory and nobody complains "oh gosh I got too much memory" much to me.
- Someone 3y ago> and you can get 4GB more memory than the prior maxiumum which frankly seems a small jump FTA: He speculates the M3 variant Apple is testing is the base-level M3 Pro the company plans to release sometime next year. Speculation, yes, but coming from Bloomberg, I think it’s more a bit of a controlled leak. Also, if they go from 5nm to 3nm, area-wise, that is comfortably over twice the number of transistors (5² vs 3² is 2.777…). I think a ≈doubling of memory would be possible. Even if it isn’t, 20% in a generation is nothing to sniff at. The times of huge jumps every few months are long behind us.
- ggm 3y agoThe memory isn't on the die, its soldered to the board. It's normal dimms isn't it?
- foldr 3y agoIt's not on the die, but there's no DIMM in the normal sense of the word: https://www.macworld.com/wp-content/uploads/2023/01/iFixit-M2-MacBook-Air-M2-teardown-accelerometer.jpg?quality=50&strip=all https://www.macworld.com/wp-content/uploads/2023/01/iFixit-M... (That's an M2 Macbook Air.)
- ggm 3y agoDoes it track the nm density of the core? I would think it's sourced as an independent path at whatever functional density works for the vendor at that time meeting spec. which is bus speed limited, not on-die. sorry if I mis-use terms of art, It looks to me like its unlikely to be specced to match the apparent design density of VLSI used to make the CPU.
- foldr 3y agoSure, I don't think there's any connection between the two silicon processes.