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Do you have references about AMD CPUs being more frequently bottlenecked by instruction decode despite uop caches (vs non x86)?
by fulafel 3y ago
Do you have references about AMD CPUs being more frequently bottlenecked by instruction decode despite uop caches (vs non x86)?
- tux3 3y agoI don't have any good benchmark to link to off the top of my head, but I'll handwave in the general direction of Agner Fog's guide, which is accurate in my experience (and generally a great resource): https://www.agner.org/optimize/microarchitecture.pdf https://www.agner.org/optimize/microarchitecture.pdf From the multiple "Bottlenecks in AMD Zen" sections, a common point is >The limiting fetch rate of up to 16 bytes per clock is a very likely bottleneck for CPU- intensive code with large loops Although admittedly, if your small hot loops fit in the uop cache that does largely mitigate the fetch/decode problem