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This RISC/CISC debate made a lot of sense when the "guts" of the CPU (decoder, registers, ALU, etc) occupied almost the whole chip (or box of transistors), and

This RISC/CISC debate made a lot of sense when the "guts" of the CPU (decoder, registers, ALU, etc) occupied almost the whole chip (or box of transistors), and when memory and CPU had similar speeds. The situation now is very different. The vast majority of the chip is cache. The trade-off for a much bigger decoder (or register stack, or whatever) is now just a fractionally smaller cache. And on current systems the CPU and memory operate at enormously different speeds - memory is 10+ times slower than the CPU. So to keep the CPU even vaguely busy, we have resorted to enormous caches. And we use large numbers of cores & threads, so that when one thread is waiting for memory, others may be able to run. The old game was max performance from a limited number of gates. The current situation makes such enormous numbers of gates available (even on tiny, cheap chips) that we're playing an altogether different game.

sweetjuly 3y ago
While area is now very cheap, power and thermal is more of an issue than ever. Huge d/i caches are doable since they save power, huge arrays of decoders not so much. The CISC-RISC debate wasn't just based on area; everyone back then also saw the direction that scaling was taking us.
branko_d 3y ago
> memory is 10+ times slower than the CPU The difference is much greater than that - one uncached RAM access can take hundreds of CPU cycles.
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audunw 3y ago
The interesting part of RISC vs CISC now isn't the complexity of the instructions or whether they're variable or fixed length. Both ARM and RISC-V has aspects that could be considered CISC-like in that regard. The interesting difference is the memory model of the instructions. What kind of dependencies between instructions you have to keep track of when decoding them. If I understand correctly, that's the thing that makes it very hard to scale x86 wider, as talked about in another top comment in this thread. The decoder doesn't necessarily scale linearly with the width of the decoder. Since ARM and RISC-V hasn't traditionally competed in the very high end ultra-wide superscalar CPU space until recently, it's possible that we're not going to see x86 held back until more advanced ARM/RISC-V manages to scale to a wider architecture than what x86 is reasonably capable of.

sweetjuly 3y ago

While area is now very cheap, power and thermal is more of an issue than ever. Huge d/i caches are doable since they save power, huge arrays of decoders not so much. The CISC-RISC debate wasn't just based on area; everyone back then also saw the direction that scaling was taking us.

branko_d 3y ago

> memory is 10+ times slower than the CPU The difference is much greater than that - one uncached RAM access can take hundreds of CPU cycles.

deleted 3y ago
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audunw 3y ago

The interesting part of RISC vs CISC now isn't the complexity of the instructions or whether they're variable or fixed length. Both ARM and RISC-V has aspects that could be considered CISC-like in that regard. The interesting difference is the memory model of the instructions. What kind of dependencies between instructions you have to keep track of when decoding them. If I understand correctly, that's the thing that makes it very hard to scale x86 wider, as talked about in another top comment in this thread. The decoder doesn't necessarily scale linearly with the width of the decoder. Since ARM and RISC-V hasn't traditionally competed in the very high end ultra-wide superscalar CPU space until recently, it's possible that we're not going to see x86 held back until more advanced ARM/RISC-V manages to scale to a wider architecture than what x86 is reasonably capable of.