2 ms·
x86 is not a very CISCy CISC, compared to VAX or 68020. x86 has relatively simple addressing modes and often limits instructions to one memory operand. It woul
by fanf2 4y ago
x86 is not a very CISCy CISC, compared to VAX or 68020. x86 has relatively simple addressing modes and often limits instructions to one memory operand.
It would be interesting to see how well a modern VAX or 68k could compete with x86 and ARM.
- ggm 4y agoI came here to say much the same. The labels were defined (CISC/RISC) in a time of different costs and CPUs. Roll forward, and both RISC has become more complex and CISC has adopted many features of RISC. I would have loved to see more clear signs of how much L1/L2 cache plays here, and the interconnect between cores. I suspect we're now well down a path where writing code to fit into L1 and writing code to balance load across cores has more importance than anything else. (not a VLSI or ISA person btw)