5 ms·
Author here if anyone has 8086 questions...
by kens 3y ago
Author here if anyone has 8086 questions...
- bonzini 3y ago> Out 11 indicates instructions where bit 7 is the byte/word indicator Wouldn't that be bit 0?
- sanqui 3y agoThis is tangential, but seeing the 8086 opcode table organized in octal groups made me realize the same applies for the instruction set of the Z80 (my home CPU). Your articles are always very insightful, thank you!
- stevekemp 3y agoZilog and Intel have a lot of crossover in that regard, due to engineers moving from one to the other. There's a whole lot of documentation on decoding instructions for the z80 which makes these octal relationships clear. One good site is http://z80.info/ http://z80.info/, for example. (I started coding on the Z80, and nowadays tinker with a single-board machine running CP/M on one.)
- bonzini 3y agoThe 8080 has 7 registers and a single addressing mode for accumulator-based instructions (which is most of them), therefore base-8 organization is pretty natural. Likewise for 8086 which has 8 registers and 8 ways to use registers to form an addressing mode (with absolute addressing and three different displacement modes, there would be 8*3+1=25, but they sacrificed [BP] to fit everything in MOD={00,01,10}). Of course one wonders if the choice of 8 registers and 8 addressing mode was due to some kind of fixation with base 8, or vice versa. Compared to the 6809, the 6502 or the 68000, the biggest reminiscence of the Z80 is the difference between AX/CX/DX/BX having 8-bit parts and SI/DI/SP/BP not having them. Though the low/high parts of IX and IY were accessible on the Z80 via undocumented opcodes (maybe even SP? I don't remember).
- ngneer 3y agoAny insight into how CALL/RET opcodes were decided or why they are in different groups? Is it merely that these would have been free opcodes? Digging up some stack history: https://en.wikichip.org/wiki/intel/mcs-4/4004 https://en.wikichip.org/wiki/intel/mcs-4/4004 4004 - 4-level stack using PCx registers, with JMS/BBL to transition to/from subroutine, causing return address pushes/pops (deepest ones lost); 4040 – 8-level stack using PCx registers; 8008 – 8-level stack using AS call levels; 8080 – stack pointer register (SP) ...
- kens 3y agoI think CALL/RET are mostly arbitrary, where there were free opcodes. But RET iw and RETF iw share the microcode, using bit 3 of the instruction to distinguish them. So they need to have opcodes differing only in bit 3.
- ngneer 3y agoCool, thank you! Interesting about the encoding proximity for flows with shared microcode. I wonder if that simplified the decoder.
- agalunar 3y agoWhy did the 8086 have the LOCK prefix? I think of it as being mostly useful in parallel contexts, e.g. lock cmpxchg for an atomic compare and swap. But the 8086 was a single core, single thread processor, and I'd be surprised if it were used in multiprocessor machines. Oh! did it have anything to do with the 8087?
- userbinator 3y agoIt was designed with the intention of being used in SMP configurations too, and I believe some industrial control systems were built that way.
- monocasa 3y agoIn addition to what was said about the viability of SMP, the lock prefix is handy for interrupt safe ops without wholesale disabling interrupts.