3 ms·
Indirect addressing, including memory indirect addressing, which takes a base address (register), an index (register), a size (immediate), two offsets (immediat
by klodolph 3y ago
Indirect addressing, including memory indirect addressing, which takes a base address (register), an index (register), a size (immediate), two offsets (immediate), and an address stored in memory somewhere.
You could, in one single instruction,
struct B {
int x, y, z;
};
struct A {
int a, b, c;
struct B *ptr;
};
void func(struct A *array, int i) {
array[i].ptr->z = 3;
}
Unless I am remembering how it works incorrectly.
- bewaretheirs 3y agogodbolt doesn't seem to think so. This is a little closer: https://godbolt.org/z/5K4MEYe31 https://godbolt.org/z/5K4MEYe31 and IIRC there was also the "LEA" instruction ("Load Effective Address") which stored the computed memory address instead of fetching/storing to that address. And I believe some compilers would (ab)use that to do math as well (though this was complicated by the aX/dX register split)
- mras0 3y agoThe addressing modes do exist on 68020+ (https://www.nxp.com/files-static/archives/doc/ref_manual/M68000PRM.pdf https://www.nxp.com/files-static/archives/doc/ref_manual/M68... section 2.2), but I don't think any compiler will generate them (even with -mcpu=68020) as I think they're not actually faster than doing it the normal way (even if that costs a register), maybe slower, but I'd have to check the cycle counts. EDIT: Yeah, so if I'm not misreading MC68020UM the memory indirect mode is slower move.l #3,([6,a0,d0.l*8],4) ; 9 cycles best case vs. move.l 6(a0,d0.l*8),a0 ;4 move.l #3,4(a0) ; 3
- mras0 3y agoOnly supported on 68020+ though, but yeah think it would be something like move.l #3,([6,a0,d0.l*8],4) (scale only goes up to 8 though)