>SRAM is affected, which is why SRAM arrays should always use SECDED ECC. How many SRAM arrays exist in electronics we use every day that don't have, at minimu

>SRAM is affected, which is why SRAM arrays should always use SECDED ECC. How many SRAM arrays exist in electronics we use every day that don't have, at minimum an error detection and reset mechanism? What about hardware registers that aren't structured as 2D arrays, how often are those protected? Things like buses and counters are at least somewhat vulnerable too.