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432-Core RISC-V European Processor Designed for Use in Space Taped Out
- Proven 3y ago[dead]
- ummonk 3y agoDo the AI cores use a standardized API? Is it an extension to the RISC-V set? Is the API similar to normal CPU multithreading, or more like GPU kernels or SIMD?
- sneakerblack 3y ago> Occamy has a lightweight 32-bit CPU core that acts more as a control chip, and it is responsible for rerouting tasks to the AI cores, which are extensions to the instruction set architecture. Seems like the latter
- monocasa 3y agoIt's RISC-V, both the control core and the compute cores. Has a few extensions on the compute side for loading the register file from DMA and chaining FPU ops with no core front end babysitting. Honestly reminds me a lot of GPU architectures, though not quite as wide per compute core (so not as wide compared to a SM or wavefront). Probably legitimately makes for a very nice HPC chip all else being equal.
- dpeckett 3y agoI hope someone picks up the architecture and brings it to the wider market. Would be great to see some opensource hardware AI accelerator options. Looking more closely at snitch, unfortunately it looks like the two largest contributors have already left the project. Perhaps they can keep momentum but industry poaching remains an issue for ESA.
- fer 3y agoIt reminds me more of the (now abandoned) Xeon Phi line of processors.
- Symmetry 3y agoParts of it reminded me of the Cell too.
- sanxiyn 3y agoIt is a set of extensions to the RISC-V instruction set. Extensions (Xssr, Xfrep, Xdma) are documented here: https://pulp-platform.github.io/snitch/rm/custom_instructions/ https://pulp-platform.github.io/snitch/rm/custom_instruction...
- panick21_ 3y agoRISC-V does not yet have an official 'AI' instruction set extension. There is a working group thinking about different extensions to help AI. RISC-V has Vector instruction that do help accelerate many workloads but they are far more general. Many RISC-V companies have their own AI instructions, there is no standard as this is still a research topic. There is also no standard for GPU, there is a graphics workgroup as well.
- galangalalgol 3y agoMy understanding was that risc-v intends to support vector processing, not simd to avoid instruction bloat and for portable binaries. There is already a letter reserved for packed simd in the isa naming convention though (P). Are there actually boards I can buy that support either? Will llvm generate either? I look forward to seeing how it works.
- brucehoult 3y agoThere are no chips/boards implementing the standard P extension as it is nowhere near finalised. The base for the proposed P extension came from Andes who have been shipping their custom packed SIMD ISA on their own NDS32 and then RISC-V cores for a number of years. There are currently no chips or boards implementing RVV 1.0. There seems to be a prospect for a board with a single core 1.6 GHz dual-issue in-order core (C908) implementing RVV 1.0 for $30-$40 perhaps towards the end of the year. https://twitter.com/SipeedIO/status/1654055669774036993 https://twitter.com/SipeedIO/status/1654055669774036993 There have been chips and boards implementing the mid-2019 RVV draft 0.7.1 since the first Allwinner D1 board with single 1.0 GHz 64 bit C906 core in April 2021 (and a lot more since). In the last few months we have seen three new chips implementing this vector ISA: - Buffalo Lab BL808 with a 480 MHz C906 (plus a couple of 32 bit cores) and 64 MB of PSRAM: Pine64 Ox64, Sipeed M1s - THead TH1520 with 4x 2.0 GHz OoO C910 cores similar to Arm A72 in e.g. Pi 4: Lichee Pi 4A, Roma laptop (supposedly), other as yet unannounced boards coming soon - Sophon SG2042 with 64x 2.0 GHz OoO C910 cores, 64 MB L3 cache, 32x PCIe gen 4, four DDR channels. I've been using one of these remotely via ssh. The first retail machine with it, the Milk-V "Pioneer" is available for preorder in China now, reportedly Crowdsupply soon. RVV 0.7.1 is very similar to 1.0, but there were a few changes in between that make them incompatible (which is expected because draft specs were never expected to be widely implemented .. but here we are). SOME carefully-written code is binary compatible between them e.g. memcpy(), but in general a little usually trivial conversion is necessary.
- monocasa 3y agoMore details here: https://pulp-platform.org/docs/STW2022_kgf.pdf https://pulp-platform.org/docs/STW2022_kgf.pdf Here's the source for the compute CPU core: https://github.com/pulp-platform/snitch https://github.com/pulp-platform/snitch
- pavlov 3y agoI wonder what the cache coherency story is. At a quick glance, the presentation mentions DMA and local scratchpad memory. Is this similar in approach to the IBM/Sony/Toshiba Cell processor which also had one general purpose core in charge of a fleet of compute-oriented cores?
- EuropeOverlords 3y agoThis has FP64 FLOPS same as RTX4080 does.
- endliner 3y agoThis is a somewhat misleading metric, seeing how FP64 compute isn't a priority for consumer GPUs. Still, it's great to see that at least some facet of modern GPUs can be replicated independently without using an ridiculously oversized die. There may yet be hope for some new GPU startup.
- pavlov 3y agoWhich is nice, but doesn't really answer my question? There's a tremendous usability difference between "X flops and all the different types of cores can read and write to unified memory with cache coherence" (as on Apple Silicon) vs. "X flops but you need to carefully orchestrate chunks of data in and out of local scratchpad buffers" (as on the Cell).
- Symmetry 3y agoThe FPU/memory interleaving reminds me of ARM's Helium instructions. Which makes sense given the flock of chickens approach. It's great to see people developing practical architectural innovations for their own use cases like this guy.
- rkagerer 3y agoCurious, what sort of applications call for lots of AI horsepower in space?
- petra 3y agoCommunication from space is a big constraint. An AI chip could analyze and compress sensor data locally. It's also could be used for DSP for the communication algorithm.
- lonelyasacloud 3y agoComms and control; signal corruption and delay will increase as the distance increases. For comms, that means either more transmission power from a spacecraft that is likely to have been travelling for years, if not decades. Bigger ground or space-based receivers. Or much, much more cost-effectively, reducing bandwidth by adding more bits in error correction. QED using ai to transmit only interesting information becomes attractive. While for control, it takes between five to twenty minutes for a signal between Earth and Mars, and between Earth and Voyager 1, it's currently twenty-one hours. Adding better control and the ability to cope with more eventualities to a craft that will fly itself in poorly understood situations reduces the cost of trying to achieve a reasonable likelihood of mission success [0]. [0] The alternative being to send one - or more - simpler but still massively expensive craft to determine the missing data ahead of time (and hope it doesn't change).
- jakeinspace 3y agoFor satellites doing high-res earth observation of astronomical observation, detecting noteworthy frames on-satellite to prioritize for downlink can save a lot of bandwidth. Downlink is often only possible during certain parts of orbit (unless geostationary), with long blackout periods. Being able to run a moderately big CNN le transformer to spot ships, troop movements, methane leaks etc on satellite would be worth a some extra power and weight.
- CrampusDestrus 3y agoA rover traversing a far away planet has numerous minutes of lag. Autonomous drive is a very helpful feature, for which AI is needed
- petra 3y agoWhat is a the manufacturing process for this ? How is it radiation hardened ?
- chasil 3y agoGlobalfoundaries 12nm, hardening not reported. "The chip is being manufactured by Globalfoundries on the 12-nanometer low-power process."
- sanxiyn 3y agoThe article says: > The chip is being manufactured by Globalfoundries on the 12-nanometer low-power process. As far as I can tell it is not radiation hardened yet. I think what the article is trying to say is that since it is an open source hardware, ESA is not dependent on the vendor for radiation hardening.
- formerly_proven 3y agoGlofo 12nm is an FD-SOI process, which is inherently less sensitive to radiation than normal bulk CMOS. Since the substrate is an isolator SOI devices are also generally immune to latchup.
- streakfix 3y agoPack it inside lead?
- danparsonson 3y agoOh yeah, great - put the AI overlords in space where we can't easily reach them and shut them down when they go crazy and start dropping satellites on us.
- detrites 3y agoWell if each satellite could kill maybe 2-3 people that'd be a whopping AI genocide of around 20k innocents, in the final battle of AI vs human.
- danparsonson 3y agoPff you're not thinking like an evil AI - you start with the GPS satellites and ruin most of transportation at the same time!
- speed_spread 3y agoAlso makes it possible for aliens to stay hidden by appearing "uninteresting" to the probe's predictable AI.
- danparsonson 3y agoA note to anyone who's unsure - this was intended to be a joke; I missed the mark I guess
- elzbardico 3y agoHN sometimes takes things very literally
- danparsonson 3y agoThank you; so much is easily lost in written communication, I should be clearer.
- j-pb 3y agoIt's weird that they are using SystemVerilog given that EU projects tend to heavily favour VHDL in my experience.
- deleted 3y ago[deleted]
- nunuvit 3y agoThey wouldn't use a chip like this for anything safety-critical, which is the main reason for using well-established tools and techniques. Fielding new technology in a less critical role is an opportunity to establish new tools as well.
- j-pb 3y agoI would come to the same conclusion if they had used something like Chisel or another of the new HDLs that are based on higher level languages and metaprogramming, but Verilog is arguably the older language when compared with VHDL.
- nunuvit 3y agoI probably shouldn't have said "new" without explaining myself more. For safety- and mission-critical applications (SC and MC), Verilog is more established in the US, and VHDL is more established in Europe. For SC, a tool doesn't get any points unless you've used it yourself, so the fact that they occupy the same role and have similar pedigree elsewhere is nearly irrelevant. Each tool permeates all the way down to the less critical roles in order to establish it for more critical use by those specific companies and government agencies. That's how these tools get entrenched in different places. For MC, you can bring things into your company or agency that are relatively new to your organization or less used in your organization. This processor would at most be used for MC and it's a significant new capability, so it's not all that weird.
- j-pb 3y agoThat argument essentially boils down to "they wanted to try it", but I don't think that it explains why they would want to try it. Verilog is arguably worse from a verification standpoint, which is afaik the main reason why VHDL won out in Europe. Pretty much every academic hardware working group that I encountered is also a formal verification working group.
- xupybd 3y agoThey didn't talk about radiation hardening. Is this chip safe to use in space? I thought a chip that dense would be vulnerable to cosmic rays?
- 2OEH8eoCRo0 3y agohttps://en.wikipedia.org/wiki/Ingenuity_(helicopter) https://en.wikipedia.org/wiki/Ingenuity_(helicopter) > Ingenuity, also called Ginny, is a small robotic helicopter operating on Mars. > The helicopter uses a Qualcomm Snapdragon 801 processor Edit: There is a way to detect and recover from these types of errors. They appear to be able to run the computation on a number of cores with a voter to check for consistency. Slide 41 (PDF warning): http://microelectronics.esa.int/riscv/rvws2022/presentations/05-ESA_PULP.pdf http://microelectronics.esa.int/riscv/rvws2022/presentations...
- sjburt 3y agoIngenuity had a Snapdragon, but there was also a redundant pair of arm r5f microcontrollers (which are also lockstepped dual-core processors, so quadruple redundancy) where the flight controllers were, and a rad-tolerant FPGA (proasic) that watchdogged everything else. The Snapdragon was used for less critical code such as imaging and comms. https://rotorcraft.arc.nasa.gov/Publications/files/Balaram_AIAA2018_0023.pdf https://rotorcraft.arc.nasa.gov/Publications/files/Balaram_A...
- Symmetry 3y agoAlso, thanks to the thin atmosphere and lack of a magnetic field Mars's surface is about 50 times more radioactive than the Earth's, but it's still no as bad as space out past the Van Allen belts
- EuropeOverlords 3y agojoke : They do not have to care about error every 67 billionth callculation that much, AI is hallucinating enough.
- _a_a_a_ 3y ago
- nomercy400 3y agoIs there also a non-space version? A fully-european competitor to x86 and arm sounds healthy.
- EuropeOverlords 3y ago"traditional" vendors provide ** in realms of Intelligence agencies..., so these "traditional" vendors are very hard to replace with open source variants. just look what apple had to do just for example in terms of scanning all your pictures for ** or **, just to not to be ordered by federation to do things which are required to disclose to shareholders...
- EuropeOverlords 3y agoand still "comply" with requirements for "cooperation with law enforcement".
- 7speter 3y agoA lot of talk about ai cores. Is that just a fancy way of saying the chip is good at making parallel computing? Also is this chip only really suitable for missions or is this chip also suitable for something like an orbiting datacenter? Or would the earths magnetosphere be able to protect terrestrial chips in orbit from radiation?
- b20000 3y agothe problem is that if you are a small time device maker the fpga you need to replicate this design would cost so much that the product becomes unaffordable. and you can’t run it fast enough unless you turn it into an asic? i have been looking for ways to create an 8 core risc V cpu in a cheap fpga (sub $10) while making it run fast enough to compete with ARM cortex A chips. as far as i can tell this still can’t be done. the people who design the chips often make poor choices regarding peripherals and features. this is because they are not the end users who are the software engineers. so what would be really interesting is to no longer need to create asics and just as a software developer design the cpu you want and program it into an fpga while being competitive cost wise.
- gianna-paulin 3y ago[dead]