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Verilog/VHDL isn't so much a programming language as a hardware definition language and woe to anyone who conflates the two. Verilog/VHDL is it's own class of t

Verilog/VHDL isn't so much a programming language as a hardware definition language and woe to anyone who conflates the two. Verilog/VHDL is it's own class of thing and sits outside of software languages.

dgacmu 3y ago
Without weighing in on exactly if it is or isn't a "language", I think VHDL/verilog absolutely have a place in the list and are a fantastic thing for (some, particularly lower-level interested) programmers to learn precisely because it's such a different way of thinking about programming and huge piles of heterogeneous behavior happening concurrently. It really cooked my head for the first week or two and I think I came out the other side better. (I hated writing VHDL with a passion. It was painful medicine for a software person used to algol-style languages. But I'm really glad I did.)
denotational 3y ago
This is an overly simplistic take in my opinion. From a PLT perspective they are programming languages just like any other, and one can analyse them using the same machinery (formal semantics, typically of the operational style) as any other programming language. Just because they are not even close to an imperative paradigm doesn’t make them any less of a programming language. They are reasonably close to process-calculus/message-passing languages in the sense that you can treat a Verilog process as a receiver listening to channels that contain messages generated when nets/variables are driven. I agree that a software developer who tries to write Verilog as if it were C will very quickly run into trouble, but that isn’t because it’s not a programming language; it’s because it’s a programming language with a similar syntax to C but with drastically different semantics.
colanderman 3y ago
They're languages for descriptions of reactive dataflow. That they happen to specialize in dataflow which is synthesizable as hardware doesn't change that they're programming languages. (Yes, it's easy to accidentally write unsynthesizable code in them -- but similar issues hold true for many declarative languages.)

dgacmu 3y ago

Without weighing in on exactly if it is or isn't a "language", I think VHDL/verilog absolutely have a place in the list and are a fantastic thing for (some, particularly lower-level interested) programmers to learn precisely because it's such a different way of thinking about programming and huge piles of heterogeneous behavior happening concurrently. It really cooked my head for the first week or two and I think I came out the other side better. (I hated writing VHDL with a passion. It was painful medicine for a software person used to algol-style languages. But I'm really glad I did.)

denotational 3y ago

This is an overly simplistic take in my opinion. From a PLT perspective they are programming languages just like any other, and one can analyse them using the same machinery (formal semantics, typically of the operational style) as any other programming language. Just because they are not even close to an imperative paradigm doesn’t make them any less of a programming language. They are reasonably close to process-calculus/message-passing languages in the sense that you can treat a Verilog process as a receiver listening to channels that contain messages generated when nets/variables are driven. I agree that a software developer who tries to write Verilog as if it were C will very quickly run into trouble, but that isn’t because it’s not a programming language; it’s because it’s a programming language with a similar syntax to C but with drastically different semantics.

colanderman 3y ago

They're languages for descriptions of reactive dataflow. That they happen to specialize in dataflow which is synthesizable as hardware doesn't change that they're programming languages. (Yes, it's easy to accidentally write unsynthesizable code in them -- but similar issues hold true for many declarative languages.)