> The FPGA on the other hand has the output ready one clock cycle after the inputs stream in, and can have many such operations in parallel. One might ask, why

> The FPGA on the other hand has the output ready one clock cycle after the inputs stream in, and can have many such operations in parallel. One might ask, why are cpus not being replaced by FPGAs? You need to be careful with interpreting cycle counts as execution time. A naive operation on an FPGA may take a single cycle because the author has asked for that, rather than constructing and using a pipelined multi-cycle ALU [1]. Therefore the design tool will synthesize a layout that performs the operation in a single cycle, but the cycle time (and thus clock frequency for that portion of the layout) will be limited by however long that operation needs to complete, and will be much longer than the cycle time of the CPU you are comparing against. Note that a CPU almost certainly has "better" ALUs than those you'd get on an FPGA - optimized fixed-function circuits can always be faster than their generic programmable equivalents - the advantage of the FPGA is that you can have only (and more of) the operations you need, running in parallel as many times as the device will support. You could make a CPU by which every instruction (even very complicated vector instructions like AVX or SVE) was completed entirely in a single cycle, but that cycle itself would be very long, and all of the incredible throughput benefits of pipelined execution would be lost. [1] Pretty much all of the vendor design tools can instantiate an ALU for your device, given parameters like # of bits, operation types, # of cycles, etc.