People have mentioned that the RAM is the logic (or at least most of it), but you are correct that it's only half the challenge: the routing of signals between

People have mentioned that the RAM is the logic (or at least most of it), but you are correct that it's only half the challenge: the routing of signals between logic blocks is also a huge part making an FPGA: there's a bunch of painful tradeoffs between flexibility, cost, and performance (and predictability of signal propagation). It's probably the area with the most secrecy from the vendors, as well. But broadly speaking there's usually a hierarchy of potential connections, from many local connections which can connect adjacent logic blocks together to a smaller number of connections which can jump longer distances (though you can always push a signal by hopping between logic blocks, this takes more resources and is slower), and a few connections which cover the whole of the chip, usually used for clock signals (and there's some extra stuff to care about here, since you usually want the clock signal to arrive to every flip-flop at the same time, you need to design the shape of these connections carefully)