one big problem is memory. basic cpus have alot of facilities for high-speed synchronous interface with DRAM, and truly vast amount of resource for cache. part

one big problem is memory. basic cpus have alot of facilities for high-speed synchronous interface with DRAM, and truly vast amount of resource for cache. partially as a result, a good model for compiling code to fpgas uses a dataflow paradigm, since we don't need to serialize all operations through a memory fetch, cache, or even register file. if we hadn't decided to move all our computing to the cloud, I suspect fpga accelerator boards for applications which map well to that model would have some traction in specialized areas. signal processing is definitely one such.