"That isn't and wasn't the thing that RISC processors reduced." Yes, it was, it literally was. Which addressing mode are you referring? Address calculation mod

"That isn't and wasn't the thing that RISC processors reduced." Yes, it was, it literally was. Which addressing mode are you referring? Address calculation mode, or operand accessing mode? Because you have NO IDEA what you're taking about. RISC original idea was all instructions would execute in a single tick. They had a load-store design, everything was hard-wired, and there would be no multi-step operations, and there would be ZERO microcode. * ARM has microcode, everything is not hard-wired * ARM has multi-tick instructions The only thing ARM has that is RISC is load-store, and now there are multiple prefetch load-stores, which absolutely goes against the grain of original RISC mentality. By RISC processor standards of the 1970s-1990s, ARM is not a RISC processor. A load-store design is where operations are loaded into the registers. What this means is you have to load the operands into the registers, they don't come from memory. A register-memory design is one where the operands can come from memory as well. This was the case for CISC in the 1980s, and 1990s. Not the case anymore. AVX is great example, Certain instructions can, and cannot be executed in this manner. The ARM has predication, which IS NOT RISC. The ARM uses microcode, which is not RISC. There are no pure RISC processors being designed today, in-which the original concepts Hennessy outlined. The lines between architectures are blurred. I like how you take one thing, and then claim that makes it RISC. No it doesn't. The 80486 CISC was more RISC like than the modern ARM. Can goal posts move? Yes. But what exists today are blurred amalgamations of both CISC and RISC. There are no pure CISC CPU's, as there are no pure RISC CPU's.