> all instructions should be the same size in classic RISC. IIRC yes, and also I think it's a matter of (at least in classical RISC designs) all instructions b

> all instructions should be the same size in classic RISC. IIRC yes, and also I think it's a matter of (at least in classical RISC designs) all instructions being fairly simple and being of close enough latency that, for the most part, instructions had a very close delay. Contrast to something like x86 where some instructions were fast but others were far far slower. The advantage of this was that pipelines would be easier to do, and while you would need more instructions to complete some tasks, the simplified processor designs would be easier to improve upon. Oh, the other advantage was, this was easier to pipeline but would in many cases result in the dreaded 'branch delay slot' where an instruction after a branch would be done, even if the branch was taken[0] And, in some ways that proved true in it's own right. The AMD K5 was based on an AMD Am29000 CPU with an X86 Decoding front end, (The NexGen 5x86 was as well, and did it -first- but AFAIK had a more 'purpose built' RISC core, The Pentium Pro I assume also had a 'purpose built' core, so the lineage is, at least most -easily- traceable with the K5.) [0] - The connection between Branch Delay Slots in RISC architectures and speculative execution and pipeline vulnerabilities such as Spectere/Meltdown feels under explored, IMO there is a relation.