25 ms·

I'm pretty sure the first generation MIPS/ARM/etc had off chip (but very close) caches

dfox 3y ago
The point there is that for the “traditional” RISC pipeline you need to read 32b worth of instruction from somewhere every cycle. You cannot do that if the only thing you have is one 32b wide bus to the outside world. First ARMs solved this by somewhat complex sequencer and not that deep pipelining. Another thing is that anything off-chip is going to be at least two clock cycles as you do not want the however fast off-chip memory to be part of your critical path. But well, many RISC designs had off-chip SRAM caches, sometimes even ridiculously large (PA-RISC is a prime example).
- Taniwha 3y ago
  You can run a piped i-cache faster (with a branch penalty ... but those machines also often had delay slots ...)
laurencerowe 3y ago
I think ARM2 (the version used in the first Archimedes computers) had no cache on or off chip. ARM3 had 4KB of on-chip cache. > Although the ARM2 employed by current models could reportedly be run at 20 MHz, it was only ever run at 8 MHz due to external limitations, these being the speed of the data bus and of the "relatively slow", but correspondingly relatively inexpensive, RAM devices in use. The ARM3 incorporated a 4 KB on-chip combined instruction and data cache, loosening such external constraints and thus permitting the processor to be run productively at the elevated 20 MHz frequency. https://en.wikipedia.org/wiki/Acorn_Archimedes#ARM3_upgrades https://en.wikipedia.org/wiki/Acorn_Archimedes#ARM3_upgrades Though it did support page mode DRAM. > Another change, and among the most important in terms of practical real-world performance, was the modification of the instruction set to take advantage of page mode DRAM. Recently introduced, page mode allowed subsequent accesses of memory to run twice as fast if they were roughly in the same location, or "page", in the DRAM chip. Berkeley's design did not consider page mode and treated all memory equally. The ARM design added special vector-like memory access instructions, the "S-cycles", that could be used to fill or save multiple registers in a single page using page mode. This doubled memory performance when they could be used, and was especially important for graphics performance. https://en.wikipedia.org/wiki/ARM_architecture_family#Design_concepts https://en.wikipedia.org/wiki/ARM_architecture_family#Design...
- dfox 3y ago
  The instructions that took advantage of FPM DRAM already existed in ARM1, only the implementation was different. And exactly these instructions (that essentially do the RISC/SPARC-like register window shift as an explicit operation) are the reason why ARM should be ACM, as in Acorn CISC Machine.
  - laurencerowe 3y ago
    I ignored the ARM1 as I thought it was more of a prototype. > ARM1 was distributed as an evaluation system and was never commercialized. https://en.wikichip.org/wiki/acorn/microarchitectures/arm1 https://en.wikichip.org/wiki/acorn/microarchitectures/arm1

dfox 3y ago

The point there is that for the “traditional” RISC pipeline you need to read 32b worth of instruction from somewhere every cycle. You cannot do that if the only thing you have is one 32b wide bus to the outside world. First ARMs solved this by somewhat complex sequencer and not that deep pipelining. Another thing is that anything off-chip is going to be at least two clock cycles as you do not want the however fast off-chip memory to be part of your critical path. But well, many RISC designs had off-chip SRAM caches, sometimes even ridiculously large (PA-RISC is a prime example).

Taniwha 3y ago
You can run a piped i-cache faster (with a branch penalty ... but those machines also often had delay slots ...)

laurencerowe 3y ago

I think ARM2 (the version used in the first Archimedes computers) had no cache on or off chip. ARM3 had 4KB of on-chip cache. > Although the ARM2 employed by current models could reportedly be run at 20 MHz, it was only ever run at 8 MHz due to external limitations, these being the speed of the data bus and of the "relatively slow", but correspondingly relatively inexpensive, RAM devices in use. The ARM3 incorporated a 4 KB on-chip combined instruction and data cache, loosening such external constraints and thus permitting the processor to be run productively at the elevated 20 MHz frequency. https://en.wikipedia.org/wiki/Acorn_Archimedes#ARM3_upgrades https://en.wikipedia.org/wiki/Acorn_Archimedes#ARM3_upgrades Though it did support page mode DRAM. > Another change, and among the most important in terms of practical real-world performance, was the modification of the instruction set to take advantage of page mode DRAM. Recently introduced, page mode allowed subsequent accesses of memory to run twice as fast if they were roughly in the same location, or "page", in the DRAM chip. Berkeley's design did not consider page mode and treated all memory equally. The ARM design added special vector-like memory access instructions, the "S-cycles", that could be used to fill or save multiple registers in a single page using page mode. This doubled memory performance when they could be used, and was especially important for graphics performance. https://en.wikipedia.org/wiki/ARM_architecture_family#Design_concepts https://en.wikipedia.org/wiki/ARM_architecture_family#Design...

dfox 3y ago
The instructions that took advantage of FPM DRAM already existed in ARM1, only the implementation was different. And exactly these instructions (that essentially do the RISC/SPARC-like register window shift as an explicit operation) are the reason why ARM should be ACM, as in Acorn CISC Machine.
- laurencerowe 3y ago
  I ignored the ARM1 as I thought it was more of a prototype. > ARM1 was distributed as an evaluation system and was never commercialized. https://en.wikichip.org/wiki/acorn/microarchitectures/arm1 https://en.wikichip.org/wiki/acorn/microarchitectures/arm1