3 ms·

That still doesn't make the 80486 a RISC in any sense.

by msla 4y ago

dfox 4y ago
486 vs ARM is a good comparison as both are the extreme cases of CISC and RISC designs. So much that for a real instruction mix generated by reasonably modern compilers (think gcc3 and up), 486 is actually more of an RISC than ARM with its bunch of variants of ldm/stm.
chasil 4y ago
I agree; all instructions should be the same size in classic RISC. The quantity of instructions is not as relevant.
- to11mtm 4y ago
  > all instructions should be the same size in classic RISC. IIRC yes, and also I think it's a matter of (at least in classical RISC designs) all instructions being fairly simple and being of close enough latency that, for the most part, instructions had a very close delay. Contrast to something like x86 where some instructions were fast but others were far far slower. The advantage of this was that pipelines would be easier to do, and while you would need more instructions to complete some tasks, the simplified processor designs would be easier to improve upon. Oh, the other advantage was, this was easier to pipeline but would in many cases result in the dreaded 'branch delay slot' where an instruction after a branch would be done, even if the branch was taken[0] And, in some ways that proved true in it's own right. The AMD K5 was based on an AMD Am29000 CPU with an X86 Decoding front end, (The NexGen 5x86 was as well, and did it -first- but AFAIK had a more 'purpose built' RISC core, The Pentium Pro I assume also had a 'purpose built' core, so the lineage is, at least most -easily- traceable with the K5.) [0] - The connection between Branch Delay Slots in RISC architectures and speculative execution and pipeline vulnerabilities such as Spectere/Meltdown feels under explored, IMO there is a relation.
  - chasil 4y ago
    I have always wondered this... How close was AMD's RISC to SPARC? It had register windows. Was it SPARC? https://en.m.wikipedia.org/wiki/AMD_Am29000 https://en.m.wikipedia.org/wiki/AMD_Am29000
    - speed_spread 4y ago
      It had variable-size register window which seemed to work much better than SPARC's fixed size.
- brucehoult 4y ago
  > I agree; all instructions should be the same size in classic RISC That was not true for the original RISC ISAs -- CDC6600, Cray 1, IBM 801, RISC-II -- and it is not true now for ARMv7 and RISC-V. It is only really true for RISC ISAs introduced between about 1985 and 1990. And Aarch64, where it will come to be recognised as a mistake, in time. > The quantity of instructions is not as relevant. True. A minimal but powerful ISA is a good thing, but it's not the differentiator between RISC and not-RISC. The complexity of each individual instruction is.

That still doesn't make the 80486 a RISC in any sense.

by msla 4y ago

That still doesn't make the 80486 a RISC in any sense.

dfox 4y ago

486 vs ARM is a good comparison as both are the extreme cases of CISC and RISC designs. So much that for a real instruction mix generated by reasonably modern compilers (think gcc3 and up), 486 is actually more of an RISC than ARM with its bunch of variants of ldm/stm.

chasil 4y ago

I agree; all instructions should be the same size in classic RISC. The quantity of instructions is not as relevant.

to11mtm 4y ago
> all instructions should be the same size in classic RISC. IIRC yes, and also I think it's a matter of (at least in classical RISC designs) all instructions being fairly simple and being of close enough latency that, for the most part, instructions had a very close delay. Contrast to something like x86 where some instructions were fast but others were far far slower. The advantage of this was that pipelines would be easier to do, and while you would need more instructions to complete some tasks, the simplified processor designs would be easier to improve upon. Oh, the other advantage was, this was easier to pipeline but would in many cases result in the dreaded 'branch delay slot' where an instruction after a branch would be done, even if the branch was taken[0] And, in some ways that proved true in it's own right. The AMD K5 was based on an AMD Am29000 CPU with an X86 Decoding front end, (The NexGen 5x86 was as well, and did it -first- but AFAIK had a more 'purpose built' RISC core, The Pentium Pro I assume also had a 'purpose built' core, so the lineage is, at least most -easily- traceable with the K5.) [0] - The connection between Branch Delay Slots in RISC architectures and speculative execution and pipeline vulnerabilities such as Spectere/Meltdown feels under explored, IMO there is a relation.
- chasil 4y ago
  I have always wondered this... How close was AMD's RISC to SPARC? It had register windows. Was it SPARC? https://en.m.wikipedia.org/wiki/AMD_Am29000 https://en.m.wikipedia.org/wiki/AMD_Am29000
  - speed_spread 4y ago
    It had variable-size register window which seemed to work much better than SPARC's fixed size.
brucehoult 4y ago
> I agree; all instructions should be the same size in classic RISC That was not true for the original RISC ISAs -- CDC6600, Cray 1, IBM 801, RISC-II -- and it is not true now for ARMv7 and RISC-V. It is only really true for RISC ISAs introduced between about 1985 and 1990. And Aarch64, where it will come to be recognised as a mistake, in time. > The quantity of instructions is not as relevant. True. A minimal but powerful ISA is a good thing, but it's not the differentiator between RISC and not-RISC. The complexity of each individual instruction is.