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> Modern ARM RISC processors have multitudes more instructions than that of prior generation CISC processors. That isn't and wasn't the thing that RISC process

by msla 4y ago

> Modern ARM RISC processors have multitudes more instructions than that of prior generation CISC processors. That isn't and wasn't the thing that RISC processors reduced. What was reduced was the complexity of the instructions themselves, not the number of instructions. For example, having complex addressing modes is CISC, whereas only touching the ALU in register-register operations is RISC; the theme is improved pipelineability, so you want less ALU state to have to back out if the memory operation takes a page fault. A number of things (delay slots, for example) follow from that focus on making the instructions as simple and pipelinable as possible. Here's a guy who helped design MIPS on the distinction: https://userpages.umbc.edu/~vijay/mashey.on.risc.html https://userpages.umbc.edu/~vijay/mashey.on.risc.html

ilyt 4y ago
I wouldn't call modern ARM instructions not complex either
- msla 4y ago
  That still doesn't make the 80486 a RISC in any sense.
  - dfox 4y ago
    486 vs ARM is a good comparison as both are the extreme cases of CISC and RISC designs. So much that for a real instruction mix generated by reasonably modern compilers (think gcc3 and up), 486 is actually more of an RISC than ARM with its bunch of variants of ldm/stm.
  - chasil 4y ago
    I agree; all instructions should be the same size in classic RISC. The quantity of instructions is not as relevant.
    - to11mtm 4y ago
      > all instructions should be the same size in classic RISC. IIRC yes, and also I think it's a matter of (at least in classical RISC designs) all instructions being fairly simple and being of close enough latency that, for the most part, instructions had a very close delay. Contrast to something like x86 where some instructions were fast but others were far far slower. The advantage of this was that pipelines would be easier to do, and while you would need more instructions to complete some tasks, the simplified processor designs would be easier to improve upon. Oh, the other advantage was, this was easier to pipeline but would in many cases result in the dreaded 'branch delay slot' where an instruction after a branch would be done, even if the branch was taken[0] And, in some ways that proved true in it's own right. The AMD K5 was based on an AMD Am29000 CPU with an X86 Decoding front end, (The NexGen 5x86 was as well, and did it -first- but AFAIK had a more 'purpose built' RISC core, The Pentium Pro I assume also had a 'purpose built' core, so the lineage is, at least most -easily- traceable with the K5.) [0] - The connection between Branch Delay Slots in RISC architectures and speculative execution and pipeline vulnerabilities such as Spectere/Meltdown feels under explored, IMO there is a relation.
      - chasil 4y ago
        I have always wondered this... How close was AMD's RISC to SPARC? It had register windows. Was it SPARC? https://en.m.wikipedia.org/wiki/AMD_Am29000 https://en.m.wikipedia.org/wiki/AMD_Am29000
        speed_spread 4y ago
        It had variable-size register window which seemed to work much better than SPARC's fixed size.
    - brucehoult 4y ago
      > I agree; all instructions should be the same size in classic RISC That was not true for the original RISC ISAs -- CDC6600, Cray 1, IBM 801, RISC-II -- and it is not true now for ARMv7 and RISC-V. It is only really true for RISC ISAs introduced between about 1985 and 1990. And Aarch64, where it will come to be recognised as a mistake, in time. > The quantity of instructions is not as relevant. True. A minimal but powerful ISA is a good thing, but it's not the differentiator between RISC and not-RISC. The complexity of each individual instruction is.
mst 4y ago
I tend to call ARM a load/store architecture to emphasise that difference and it seems to get my point across without derailing the conversation into a RISC-or-not debate. (Note that I'm endorsing this as working in human to human communication rather than for absolute correctness)
deviantbit 4y ago
"That isn't and wasn't the thing that RISC processors reduced." Yes, it was, it literally was. Which addressing mode are you referring? Address calculation mode, or operand accessing mode? Because you have NO IDEA what you're taking about. RISC original idea was all instructions would execute in a single tick. They had a load-store design, everything was hard-wired, and there would be no multi-step operations, and there would be ZERO microcode. * ARM has microcode, everything is not hard-wired * ARM has multi-tick instructions The only thing ARM has that is RISC is load-store, and now there are multiple prefetch load-stores, which absolutely goes against the grain of original RISC mentality. By RISC processor standards of the 1970s-1990s, ARM is not a RISC processor. A load-store design is where operations are loaded into the registers. What this means is you have to load the operands into the registers, they don't come from memory. A register-memory design is one where the operands can come from memory as well. This was the case for CISC in the 1980s, and 1990s. Not the case anymore. AVX is great example, Certain instructions can, and cannot be executed in this manner. The ARM has predication, which IS NOT RISC. The ARM uses microcode, which is not RISC. There are no pure RISC processors being designed today, in-which the original concepts Hennessy outlined. The lines between architectures are blurred. I like how you take one thing, and then claim that makes it RISC. No it doesn't. The 80486 CISC was more RISC like than the modern ARM. Can goal posts move? Yes. But what exists today are blurred amalgamations of both CISC and RISC. There are no pure CISC CPU's, as there are no pure RISC CPU's.
- msla 4y ago
  You obviously didn't read anything in the link I posted. Therefore, you have nothing to say.
georgejungle 4y ago
RISC was intended to have fewer instructions to allow reduced execution time, and higher clock speeds. The addressing mode did not define RISC, it was a method to reach the goal. That link has a lot of wrong information about RISC.
- msla 4y ago
  > The addressing mode did not define RISC, it was a method to reach the goal. And the goal was pipelineability, not having fewer instructions. > That link has a lot of wrong information about RISC. The guy who helped design one of the more successful RISC chips doesn't know anything about RISC chips? OK.

by msla 4y ago

ilyt 4y ago

I wouldn't call modern ARM instructions not complex either

msla 4y ago
That still doesn't make the 80486 a RISC in any sense.
- dfox 4y ago
  486 vs ARM is a good comparison as both are the extreme cases of CISC and RISC designs. So much that for a real instruction mix generated by reasonably modern compilers (think gcc3 and up), 486 is actually more of an RISC than ARM with its bunch of variants of ldm/stm.
- chasil 4y ago
  I agree; all instructions should be the same size in classic RISC. The quantity of instructions is not as relevant.
  - to11mtm 4y ago
    > all instructions should be the same size in classic RISC. IIRC yes, and also I think it's a matter of (at least in classical RISC designs) all instructions being fairly simple and being of close enough latency that, for the most part, instructions had a very close delay. Contrast to something like x86 where some instructions were fast but others were far far slower. The advantage of this was that pipelines would be easier to do, and while you would need more instructions to complete some tasks, the simplified processor designs would be easier to improve upon. Oh, the other advantage was, this was easier to pipeline but would in many cases result in the dreaded 'branch delay slot' where an instruction after a branch would be done, even if the branch was taken[0] And, in some ways that proved true in it's own right. The AMD K5 was based on an AMD Am29000 CPU with an X86 Decoding front end, (The NexGen 5x86 was as well, and did it -first- but AFAIK had a more 'purpose built' RISC core, The Pentium Pro I assume also had a 'purpose built' core, so the lineage is, at least most -easily- traceable with the K5.) [0] - The connection between Branch Delay Slots in RISC architectures and speculative execution and pipeline vulnerabilities such as Spectere/Meltdown feels under explored, IMO there is a relation.
    - chasil 4y ago
      I have always wondered this... How close was AMD's RISC to SPARC? It had register windows. Was it SPARC? https://en.m.wikipedia.org/wiki/AMD_Am29000 https://en.m.wikipedia.org/wiki/AMD_Am29000
      - speed_spread 4y ago
        It had variable-size register window which seemed to work much better than SPARC's fixed size.
  - brucehoult 4y ago
    > I agree; all instructions should be the same size in classic RISC That was not true for the original RISC ISAs -- CDC6600, Cray 1, IBM 801, RISC-II -- and it is not true now for ARMv7 and RISC-V. It is only really true for RISC ISAs introduced between about 1985 and 1990. And Aarch64, where it will come to be recognised as a mistake, in time. > The quantity of instructions is not as relevant. True. A minimal but powerful ISA is a good thing, but it's not the differentiator between RISC and not-RISC. The complexity of each individual instruction is.

mst 4y ago

I tend to call ARM a load/store architecture to emphasise that difference and it seems to get my point across without derailing the conversation into a RISC-or-not debate. (Note that I'm endorsing this as working in human to human communication rather than for absolute correctness)

deviantbit 4y ago

"That isn't and wasn't the thing that RISC processors reduced." Yes, it was, it literally was. Which addressing mode are you referring? Address calculation mode, or operand accessing mode? Because you have NO IDEA what you're taking about. RISC original idea was all instructions would execute in a single tick. They had a load-store design, everything was hard-wired, and there would be no multi-step operations, and there would be ZERO microcode. * ARM has microcode, everything is not hard-wired * ARM has multi-tick instructions The only thing ARM has that is RISC is load-store, and now there are multiple prefetch load-stores, which absolutely goes against the grain of original RISC mentality. By RISC processor standards of the 1970s-1990s, ARM is not a RISC processor. A load-store design is where operations are loaded into the registers. What this means is you have to load the operands into the registers, they don't come from memory. A register-memory design is one where the operands can come from memory as well. This was the case for CISC in the 1980s, and 1990s. Not the case anymore. AVX is great example, Certain instructions can, and cannot be executed in this manner. The ARM has predication, which IS NOT RISC. The ARM uses microcode, which is not RISC. There are no pure RISC processors being designed today, in-which the original concepts Hennessy outlined. The lines between architectures are blurred. I like how you take one thing, and then claim that makes it RISC. No it doesn't. The 80486 CISC was more RISC like than the modern ARM. Can goal posts move? Yes. But what exists today are blurred amalgamations of both CISC and RISC. There are no pure CISC CPU's, as there are no pure RISC CPU's.

msla 4y ago
You obviously didn't read anything in the link I posted. Therefore, you have nothing to say.

georgejungle 4y ago

RISC was intended to have fewer instructions to allow reduced execution time, and higher clock speeds. The addressing mode did not define RISC, it was a method to reach the goal. That link has a lot of wrong information about RISC.

msla 4y ago
> The addressing mode did not define RISC, it was a method to reach the goal. And the goal was pipelineability, not having fewer instructions. > That link has a lot of wrong information about RISC. The guy who helped design one of the more successful RISC chips doesn't know anything about RISC chips? OK.