3 ms·
In case one is using this info to make purchasing decisions, 3nm is a big improvement from today's leading edge 5nm process in speed, density, and power consump
by npunt 3y ago
In case one is using this info to make purchasing decisions, 3nm is a big improvement from today's leading edge 5nm process in speed, density, and power consumption [1]. We've been on 5nm variants for about 4 years now, and though each year brought gains, they were more incremental.
In Mac terms, this means M2->M3 will be bigger step up than M1->M2. Apple also delayed their next-gen raytracing GPU from last year, so it's likely that will come in as well. However with the difficulties of manufacturing, and Apple prioritizing iPhones, it's not clear whether we'll get any M3 Macs this year.
[1]: https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_3nm https://www.tsmc.com/english/dedicatedFoundry/technology/log...
- cubefox 3y agoTransistor density doesn't really matter by itself. What matters is that density influences speed, power consumption, and price. Historically all these have improved exponentially with exponentially increasing transistor density [1]. Yet: > Power and Performance were the first two metrics to “fall off” the Moore’s Law curve. Transistor power reductions slowed nearly 20 years ago—each successive node generally reduced active and standby (leakage) current, but not at the 2X reduction per node. Transistor performance gains slowed shortly after; again, each node is generally faster, but not by 2X. Moreover: > Where Moore’s Law has slowed or even reversed, however, is the cost per component. Doubling density used to cut the cost per transistor in half, which was the primary enabler of the electronics revolution. Moore’s Law meant we’d get twice the number of transistors (which were faster and less power-hungry) for the same cost. > As the chart (Fig. 2) shows, this began slowing at the 40-nm node, and virtually stopped when the industry moved to FinFETs. New nodes enable “close-to-Moore” chip-size scaling, but this is nearly completely offset by exploding wafer-fabrication costs. Various analyses show fabricated wafer costs increasing 3-5X over the 28-nm node, with 5-nm wafer costs approaching $18K each. There is also the fact that SRAM scaling has almost stopped with TSMC's N3 [2]. [1] https://www.electronicdesign.com/industrial-automation/article/21244720/electronic-design-can-advanced-materials-address-moores-law-slowdown-and-the-chip-shortage https://www.electronicdesign.com/industrial-automation/artic... [2] https://fuse.wikichip.org/news/7343/iedm-2022-did-we-just-witness-the-death-of-sram/ https://fuse.wikichip.org/news/7343/iedm-2022-did-we-just-wi...