No there are major differences. A non-exhaustive list: * Crusoe/Efficeon/... used a software JIT (called CMS) * Ran on a very custom architecture (P95/P2000)

No there are major differences. A non-exhaustive list: * Crusoe/Efficeon/... used a software JIT (called CMS) * Ran on a very custom architecture (P95/P2000) designed for JITted code with speculation (software controllable checkpoints, "assert" instructions, speculative cache, small lookup tables for translating x86 addresses to P95 etc). * It had no dynamic scheduling, reorder buffer, renaming, etc. The thesis was to eliminate the power/area hungry parts of microprocessors by having the "compiler" (= JIT) do it up front. Some things worked well (very power efficient, small die). Others less so: huge cold code penalty, limited ability to deal with large cache misses (like IA-64). Transmeta had a huge impact on the industry; Intel has officially credited Transmeta and Transmeta's LongRun with getting Intel focused on power. Both NVIDIA and "another company" have explored the CMS idea. There is so much to the Transmeta story and the failure was more of a business issue than a technical one. This was a completely new approach and Transmeta needed more iterations to refine the idea. ADD: A VLIW "instruction" (called a "molecule" in TM terminology) is compiled, fetched, issued, and (mostly) executed as a (parallel) unit. That is very very different from what modern superscalar microprocessors do. They issue instructions from many issue queues. The instructions that execute in the same cycle usually do so mostly as a consequence of data-flow and the current state of the pipeline. Large x86 instruction translated to microcode typically leads to many µops that do not execute in parallel, but are intermixed with other µops.