>Where's your actual counterargument then? At least 10b RISC-V cores shipped just last year. All of SiFive's designs offer better performance, power and area

>Where's your actual counterargument then? At least 10b RISC-V cores shipped just last year. All of SiFive's designs offer better performance, power and area than ARM's equivalent offerings. >ARM breaks down instructions into uops too. Most large implementations do today, irrespective of ISA. >Look at how ARM and x86 are very closely matched in efficiency in these studies, but MIPS (which is what RISC-V is quite similar to) is noticeably far behind MIPS had poor code density. x86 and thumb2 had good code density. amd64 (x86-64) code density degraded relative to x86, due to adding new prefix for the 64bit instructions. aarch64 degraded relative to thumb2, due to fixed instruction length. RISC-V has variable instruction length designed to avoid decoder complexity. RISC-V already has the best code density among all 64bit ISAs. It has the best code density among all 32bit ISAs too, with the draft code size extensions. Ascalon[0][1] expects performance competitive with Zen5, at lower power consumption. Both will be available in 2024. Tenstorrent's is just one of the known very high performance targeting cores under development. Others include Ventana (first chip TBA late 2023), Rivos and MIPS. RISC-V is inevitable. >Pure RISC was never good. The future of RISC-V has no limits. 0. https://youtu.be/lKEwTZmNN2Q?t=1561 https://youtu.be/lKEwTZmNN2Q?t=1561 1. https://youtu.be/QqcAC4gg2ag?t=7144 https://youtu.be/QqcAC4gg2ag?t=7144