PCIe has a continuous 100MHz clock if you don't utilize link parking power be saving mechanisms. The device should be able to lock to the host's base clock that

PCIe has a continuous 100MHz clock if you don't utilize link parking power be saving mechanisms. The device should be able to lock to the host's base clock that way, and phase offsets should be something you can resolve by measuring. Ideally computers would support consuming a PLL reference via 1GBASE-T, as that already has a need for a locked clock for TX and RX near-side cross-talk compensation, and CERN demonstrated usage of this for clock carrier distribution in their GPS-shielding tunnels. OFC integrated with PTP to accurately sync time; AFAIK they did for ns-accurate event time stamp assignment in some distributed sensor networks.