I believe from previous articles/videos from Jeff that the BAR one is at least addressable via a custom kernel or device tree that sets up a large enough BAR sp

I believe from previous articles/videos from Jeff that the BAR one is at least addressable via a custom kernel or device tree that sets up a large enough BAR space for those devices. That said I would be surprised if there's a way to easily fix the first problem in software aside from forcing constant cache flushes when dealing with MMIO registers which would be a huge undertaking and probably tank performance in ways that nobody would want since this should be handled by the controller on an as needed basis instead.