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FTA there seem to be at least 2 problems: "the Pi has problems with cache coherency on the PCI Express bus beyond 32-bits. And many (well, all nowadays) of the
by manv1 3y ago
FTA there seem to be at least 2 problems:
"the Pi has problems with cache coherency on the PCI Express bus beyond 32-bits. And many (well, all nowadays) of the drivers expect that to function."
Yeah, that's a problem.
"there were issues with the BAR (Base Address Register) space allocated on the Pi's OS."
From the GitHub link:
# The default BAR address space available on the CM4 may be too small to allow
# some devices to initialize correctly. To avoid 'failed to assign memory'
These don't look like implementation quirks, they are just flat-out errors.
- simcop2387 3y agoI believe from previous articles/videos from Jeff that the BAR one is at least addressable via a custom kernel or device tree that sets up a large enough BAR space for those devices. That said I would be surprised if there's a way to easily fix the first problem in software aside from forcing constant cache flushes when dealing with MMIO registers which would be a huge undertaking and probably tank performance in ways that nobody would want since this should be handled by the controller on an as needed basis instead.