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While discussing RAM, can someone clear up another minor conundrum for me: How does a current x86 chipset map RAM modules to linear adresses? They can differ i
by hyperman1 3y ago
While discussing RAM, can someone clear up another minor conundrum for me: How does a current x86 chipset map RAM modules to linear adresses? They can differ in size, so the mapping is probably dynamic? But I suppose an adder causes latency? Or is everything just mapped with big holes between modules, with CPU paging fixing up the mess?
- monocasa 3y agoThe mapping is more or less completely dynamic per channel. DRAM is already ~100 cycles away, so the latency of address decoding is pretty hidden.