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What is a node in this context and what does designing a new node entail? Does this design process mean TSMC can do something with ASML machines that another co

What is a node in this context and what does designing a new node entail? Does this design process mean TSMC can do something with ASML machines that another company with the same machine couldn't do?

Nokinside 3y ago
https://en.wikichip.org/wiki/technology_node https://en.wikichip.org/wiki/technology_node
rayiner 3y ago
The important thing to understand is that at the level of chip manufacturing, you’re doing advanced materials science. These aren’t just abstract logic gates and structures built out of them, such as SRAMs. At the manufacturing level, the logic gates are nano-scale 3D structures made of different materials and in different shapes. For example, at this scale, the shape of the transistor gates has a big effect on performance: https://en.wikipedia.org/wiki/Fin_field-effect_transistor https://en.wikipedia.org/wiki/Fin_field-effect_transistor. That materials science is highly guarded secret sauce in companies like TSMC. NVIDIA and Apple will tell TSMC what logic gates go where (or often at an even higher level—specifying certain SRAM blocks going here or there). But TSMC has to actually build the nano-scale material structures that comprise those logic gates. The ASML machines perform the actual photolithography. They expose the die mask to the photoresist coated silicon wafer. Using that technique, you can built up complex 3D materials incorporating different layers and shapes. But the ASML machine doesn’t know how to make a transistor. It’s kind of like a 3D printer in that way.
- phkahler 3y ago
  I like you 3d printing reference. You can have 2 people with the same printer trying to print the same part. What else goes into getting a good part? Proper bed leveling, bed heating, choice of material, part cooler, nozzle temperature, feed rate, speed, acceleration, layer thickness, infill pattern, and many other settings and choices. And that's just an off the shelf printer melting plastic...
  - ryanschneider 3y ago
    Ya this analogy really clicked with me. To really torture the analogy, Apple or any other TSMC customers hands them an .obj of their chip, and TSMC acts as the slicer and converts that into the GCode that ASML’s “printers” understand. And just like how some slicers have better overhang and infill algorithms TSMC has their own secret sauce for telling the ASML machines what to “print”. Does that expansion of the analogy work or did I just move the analogy further from the truth?
    - anon84873628 3y ago
      It's a good analogy but there's one more major aspect. The silicon wafer doesn't sit under a single "printer" the whole time. It has to be moved around between countless different machines all doing different specialized tasks. So there is a huge logistical challenge as well. It is like combining 3D printing with an international airline.
  - pen2l 3y ago
    This might be pedantic nit-picking, but: I think bed leveling/heating, nozzle temperature, choice of material, etc. are parameters that the printer manufacturer should have optimized (and, IME, good ones do). I think the end user's chief responsibility is slicing (infill patterns, layer thickness, etc. as you noted), indeed it is in this sense the end user can be said to be in the same position as Intel/Samsung, not so much the hardware maintenance but knowing the slicing tricks for getting complicated geometry to come out just right. For example, when you're making a cube, the sharp ends are places where bad things happen. When making sharp movements, the nozzle will tend to leave ugly trails and in other times cause warping. So here you can do a trick to save yourself: mouse-ears (extra material around the important edge, so that the bad artifacts happen instead on additionally-created non-core-geometry). At ground level, you use brims.
- SigmundA 3y ago
  It's also important to note how crazy the ASML EUV machines are, they each take a megawatt of power to produce about 100 watts of EUV. The infrastructure just to run these machines is staggering. TSMC uses about 5% of Taiwans total power I believe.
  - jamiek88 3y ago
    Physical size as well! The machines are two stories high! Like a bus stood vertically on its nose.
- kayson 3y ago
  > NVIDIA and Apple will tell TSMC what logic gates go where (or often at an even higher level—specifying certain SRAM blocks going here or there). That's not quite how design works; it's much much more detailed. At the end of the day, TSMC's customers send them a "GDS" file that is a complete physical representation of the die they want manufactured. It describes every top-to-bottom later of the manufacturing process. (TSMC will take the GDS layers and split them up or combine them or do other operations, depending on some process details, but the customer will also check and sign off on that). It's not just telling TSMC where to put standard cells or SRAM. And while TSMC does offer their own standard cells and SRAM, customers can and often do design and use their own. Analog/RF design is even more detailed, since that's done at an individual transistor level. TSMC is mainly in the business of design and selling a manufacturing process for making transistors not logic gates.
  - efishnc 3y ago
    So in that case there is no materials secret sauce guarded by TSMC, with the customer either submitting the GDS file with all the info, or signing off on the modified version.
    - kayson 3y ago
      Sorry my comment wasn't very clear about this. There's still secret sauce in the materials. The GDS is purely dimensional. It's just a bunch of shapes. But how those shapes get translated into actual silicon, and how various chemicals are used and in what concentrations to manipulate the silicon to make the transistors function is the secret sauce.
  - rayiner 3y ago
    I was under the impression that it’s unusual for fabless chipmakers to do transistor level design anymore, and that they mostly rely on the standard TSMC libraries. But I may be wrong about that. The critical point I was trying to make is that the ASML machine doesn’t know how to make transistors. That’s something TSMC does: https://www.anandtech.com/show/16041/where-are-my-gaafets-tsmc-to-stay-with-finfet-for-3nm https://www.anandtech.com/show/16041/where-are-my-gaafets-ts...
chasil 3y ago
The interview that I posted above discusses copper interconnects that IBM research introduced. TSMC had previously used a "spin-on" dialectic technique at a previous node, and reverted to CVD because of problems. They were able to beat all other manufacturers to market with copper interconnects (including IBM), because they avoided spin-on, which worked well in testing, but not in production. They had great luck in gaining this prior experience.

Nokinside 3y ago

https://en.wikichip.org/wiki/technology_node https://en.wikichip.org/wiki/technology_node

rayiner 3y ago

The important thing to understand is that at the level of chip manufacturing, you’re doing advanced materials science. These aren’t just abstract logic gates and structures built out of them, such as SRAMs. At the manufacturing level, the logic gates are nano-scale 3D structures made of different materials and in different shapes. For example, at this scale, the shape of the transistor gates has a big effect on performance: https://en.wikipedia.org/wiki/Fin_field-effect_transistor https://en.wikipedia.org/wiki/Fin_field-effect_transistor. That materials science is highly guarded secret sauce in companies like TSMC. NVIDIA and Apple will tell TSMC what logic gates go where (or often at an even higher level—specifying certain SRAM blocks going here or there). But TSMC has to actually build the nano-scale material structures that comprise those logic gates. The ASML machines perform the actual photolithography. They expose the die mask to the photoresist coated silicon wafer. Using that technique, you can built up complex 3D materials incorporating different layers and shapes. But the ASML machine doesn’t know how to make a transistor. It’s kind of like a 3D printer in that way.

phkahler 3y ago
I like you 3d printing reference. You can have 2 people with the same printer trying to print the same part. What else goes into getting a good part? Proper bed leveling, bed heating, choice of material, part cooler, nozzle temperature, feed rate, speed, acceleration, layer thickness, infill pattern, and many other settings and choices. And that's just an off the shelf printer melting plastic...
- ryanschneider 3y ago
  Ya this analogy really clicked with me. To really torture the analogy, Apple or any other TSMC customers hands them an .obj of their chip, and TSMC acts as the slicer and converts that into the GCode that ASML’s “printers” understand. And just like how some slicers have better overhang and infill algorithms TSMC has their own secret sauce for telling the ASML machines what to “print”. Does that expansion of the analogy work or did I just move the analogy further from the truth?
  - anon84873628 3y ago
    It's a good analogy but there's one more major aspect. The silicon wafer doesn't sit under a single "printer" the whole time. It has to be moved around between countless different machines all doing different specialized tasks. So there is a huge logistical challenge as well. It is like combining 3D printing with an international airline.
- pen2l 3y ago
  This might be pedantic nit-picking, but: I think bed leveling/heating, nozzle temperature, choice of material, etc. are parameters that the printer manufacturer should have optimized (and, IME, good ones do). I think the end user's chief responsibility is slicing (infill patterns, layer thickness, etc. as you noted), indeed it is in this sense the end user can be said to be in the same position as Intel/Samsung, not so much the hardware maintenance but knowing the slicing tricks for getting complicated geometry to come out just right. For example, when you're making a cube, the sharp ends are places where bad things happen. When making sharp movements, the nozzle will tend to leave ugly trails and in other times cause warping. So here you can do a trick to save yourself: mouse-ears (extra material around the important edge, so that the bad artifacts happen instead on additionally-created non-core-geometry). At ground level, you use brims.
SigmundA 3y ago
It's also important to note how crazy the ASML EUV machines are, they each take a megawatt of power to produce about 100 watts of EUV. The infrastructure just to run these machines is staggering. TSMC uses about 5% of Taiwans total power I believe.
- jamiek88 3y ago
  Physical size as well! The machines are two stories high! Like a bus stood vertically on its nose.
kayson 3y ago
> NVIDIA and Apple will tell TSMC what logic gates go where (or often at an even higher level—specifying certain SRAM blocks going here or there). That's not quite how design works; it's much much more detailed. At the end of the day, TSMC's customers send them a "GDS" file that is a complete physical representation of the die they want manufactured. It describes every top-to-bottom later of the manufacturing process. (TSMC will take the GDS layers and split them up or combine them or do other operations, depending on some process details, but the customer will also check and sign off on that). It's not just telling TSMC where to put standard cells or SRAM. And while TSMC does offer their own standard cells and SRAM, customers can and often do design and use their own. Analog/RF design is even more detailed, since that's done at an individual transistor level. TSMC is mainly in the business of design and selling a manufacturing process for making transistors not logic gates.
- efishnc 3y ago
  So in that case there is no materials secret sauce guarded by TSMC, with the customer either submitting the GDS file with all the info, or signing off on the modified version.
  - kayson 3y ago
    Sorry my comment wasn't very clear about this. There's still secret sauce in the materials. The GDS is purely dimensional. It's just a bunch of shapes. But how those shapes get translated into actual silicon, and how various chemicals are used and in what concentrations to manipulate the silicon to make the transistors function is the secret sauce.
- rayiner 3y ago
  I was under the impression that it’s unusual for fabless chipmakers to do transistor level design anymore, and that they mostly rely on the standard TSMC libraries. But I may be wrong about that. The critical point I was trying to make is that the ASML machine doesn’t know how to make transistors. That’s something TSMC does: https://www.anandtech.com/show/16041/where-are-my-gaafets-tsmc-to-stay-with-finfet-for-3nm https://www.anandtech.com/show/16041/where-are-my-gaafets-ts...

chasil 3y ago

The interview that I posted above discusses copper interconnects that IBM research introduced. TSMC had previously used a "spin-on" dialectic technique at a previous node, and reverted to CVD because of problems. They were able to beat all other manufacturers to market with copper interconnects (including IBM), because they avoided spin-on, which worked well in testing, but not in production. They had great luck in gaining this prior experience.