5 ms·
The memory access is through the same IOD (so memory access to main memory is fairly uniform) but there are two different CCD's, two different NUMA zones. Commu
by rektide 4y ago
The memory access is through the same IOD (so memory access to main memory is fairly uniform) but there are two different CCD's, two different NUMA zones. Communication between them is slower than communication within the CHIP. And one chip has vastly more L3 cache than the other.
- wmf 4y agoTechnically it's NUCA so treating CCXes as NUMA nodes is kind of misusing the concept. Cluster-aware scheduling might be a better way to handle it: https://www.phoronix.com/news/AMD-Linux-L2-Cluster-Scheduler https://www.phoronix.com/news/AMD-Linux-L2-Cluster-Scheduler
- sudosysgen 4y agoThe L3 caches also aren't shared between CCDs/CCXes which is an important distinction.