About I2C addressing: I've thought about the issue. That solution could fail in theory because of collisions, ie a micro-controller cannot atomically check the

About I2C addressing: I've thought about the issue. That solution could fail in theory because of collisions, ie a micro-controller cannot atomically check the assert pin and raise it if low. The project uses 1000ms + rand(0, 5000ms), which sounds big enough. I've always wondered if a solution based of multi-master I2C support could work: all childs shout a unique ID and the parent answers with their assigned I2C address. Children that do not win the arbitration will detect collisions and stop because of arbitration errors. Unsure how well it could work with many children. See https://www.i2c-bus.org/multimaster/ https://www.i2c-bus.org/multimaster/ and https://www.i2c-bus.org/i2c-primer/clock-generation-stretching-arbitration/ https://www.i2c-bus.org/i2c-primer/clock-generation-stretchi... for introductions to I2C multimaster and arbitration. The spec is of course not open. I'd be interested in discussing the topic more!