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That was exactly what came to mind as well. "Big" RISC-V performance oriented cores for apps, gobs of "small" RISC-V cores ganged together for GPU. Larrabee d

by kjs3 4y ago

That was exactly what came to mind as well. "Big" RISC-V performance oriented cores for apps, gobs of "small" RISC-V cores ganged together for GPU. Larrabee didn't work out so good, though.

PaulHoule 4y ago
Skybox is closer to the old 1970s-1980s SIMD machines like ILLIAC and the Connection Machine or (I think) the current NVIDIA, it has two sets of added instructions, one has to do with managing multiple ‘wavefronts’ (like threads) that run the same instructions with the possibility of turning some off (predication, which was deliberately left out of RISC-V, would have been a help). The other instruction control fixed function units and do fused integer multiply-adds. I don’t see any talk about vector instructions.
pavlov 4y ago
In a similar vein, two decades ago there was the Sony/Toshiba/IBM Cell processor which ganged up a general-purpose PowerPC core with a cluster of lightweight co-processing PowerPC cores called SPEs: https://en.wikipedia.org/wiki/Cell_(processor) https://en.wikipedia.org/wiki/Cell_(processor) The idea was that Cell would also act as the GPU for the PlayStation 3, but performance wasn’t good enough when the chip was finally ready, so they ended up complementing it with an Nvidia GPU. The programming model was quite difficult. The SPE cores couldn’t directly access main memory. Instead they had small local SRAM buffers (256kB I believe) that the programmer would manually fill using explicit DMA commands either from other SPEs or from main memory. Orchestrating these memory operations for high performance must have been a chore, and when you do have the data, then you have to deal with the SPE having a different architecture with no branch prediction, etc. GPUs and CUDA turned out to be a much more palatable model for general-purpose compute.
- djmips 4y ago
  With some evolution, coders adapted to this model and found approaches that both worked well and even abstractions that made working with the SPEs both effective and not as much of a chore. In an interesting turn of events it turns out that if you could architect the SPEs to perform well the same basic approach helped unlock multi core performance on x86-64.
  - kjs3 4y ago
    Somewhere I have a CellBE PCI development board (from Mercury). I should get it working again and see if it's easier to deal with now.

by kjs3 4y ago

That was exactly what came to mind as well. "Big" RISC-V performance oriented cores for apps, gobs of "small" RISC-V cores ganged together for GPU. Larrabee didn't work out so good, though.

PaulHoule 4y ago

Skybox is closer to the old 1970s-1980s SIMD machines like ILLIAC and the Connection Machine or (I think) the current NVIDIA, it has two sets of added instructions, one has to do with managing multiple ‘wavefronts’ (like threads) that run the same instructions with the possibility of turning some off (predication, which was deliberately left out of RISC-V, would have been a help). The other instruction control fixed function units and do fused integer multiply-adds. I don’t see any talk about vector instructions.

pavlov 4y ago

In a similar vein, two decades ago there was the Sony/Toshiba/IBM Cell processor which ganged up a general-purpose PowerPC core with a cluster of lightweight co-processing PowerPC cores called SPEs: https://en.wikipedia.org/wiki/Cell_(processor) https://en.wikipedia.org/wiki/Cell_(processor) The idea was that Cell would also act as the GPU for the PlayStation 3, but performance wasn’t good enough when the chip was finally ready, so they ended up complementing it with an Nvidia GPU. The programming model was quite difficult. The SPE cores couldn’t directly access main memory. Instead they had small local SRAM buffers (256kB I believe) that the programmer would manually fill using explicit DMA commands either from other SPEs or from main memory. Orchestrating these memory operations for high performance must have been a chore, and when you do have the data, then you have to deal with the SPE having a different architecture with no branch prediction, etc. GPUs and CUDA turned out to be a much more palatable model for general-purpose compute.

djmips 4y ago
With some evolution, coders adapted to this model and found approaches that both worked well and even abstractions that made working with the SPEs both effective and not as much of a chore. In an interesting turn of events it turns out that if you could architect the SPEs to perform well the same basic approach helped unlock multi core performance on x86-64.
- kjs3 4y ago
  Somewhere I have a CellBE PCI development board (from Mercury). I should get it working again and see if it's easier to deal with now.