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It reminds me of https://en.wikipedia.org/wiki/Larrabee_(microarchitecture) https://en.wikipedia.org/wiki/Larrabee_(microarchitecture) - Intel wanted to make a

It reminds me of https://en.wikipedia.org/wiki/Larrabee_(microarchitecture) https://en.wikipedia.org/wiki/Larrabee_(microarchitecture) - Intel wanted to make a GPU out of dozens upon dozens of tiny x86 cores. I think the idea was start building an x86 moat around CUDA (ha).

panick21_ 3y ago
One of the architects of Larrabee was very involved in RVV. He has some lots of good talks on Vector ISA stuff.
kjs3 3y ago
That was exactly what came to mind as well. "Big" RISC-V performance oriented cores for apps, gobs of "small" RISC-V cores ganged together for GPU. Larrabee didn't work out so good, though.
- PaulHoule 3y ago
  Skybox is closer to the old 1970s-1980s SIMD machines like ILLIAC and the Connection Machine or (I think) the current NVIDIA, it has two sets of added instructions, one has to do with managing multiple ‘wavefronts’ (like threads) that run the same instructions with the possibility of turning some off (predication, which was deliberately left out of RISC-V, would have been a help). The other instruction control fixed function units and do fused integer multiply-adds. I don’t see any talk about vector instructions.
- pavlov 3y ago
  In a similar vein, two decades ago there was the Sony/Toshiba/IBM Cell processor which ganged up a general-purpose PowerPC core with a cluster of lightweight co-processing PowerPC cores called SPEs: https://en.wikipedia.org/wiki/Cell_(processor) https://en.wikipedia.org/wiki/Cell_(processor) The idea was that Cell would also act as the GPU for the PlayStation 3, but performance wasn’t good enough when the chip was finally ready, so they ended up complementing it with an Nvidia GPU. The programming model was quite difficult. The SPE cores couldn’t directly access main memory. Instead they had small local SRAM buffers (256kB I believe) that the programmer would manually fill using explicit DMA commands either from other SPEs or from main memory. Orchestrating these memory operations for high performance must have been a chore, and when you do have the data, then you have to deal with the SPE having a different architecture with no branch prediction, etc. GPUs and CUDA turned out to be a much more palatable model for general-purpose compute.
  - djmips 3y ago
    With some evolution, coders adapted to this model and found approaches that both worked well and even abstractions that made working with the SPEs both effective and not as much of a chore. In an interesting turn of events it turns out that if you could architect the SPEs to perform well the same basic approach helped unlock multi core performance on x86-64.
    - kjs3 3y ago
      Somewhere I have a CellBE PCI development board (from Mercury). I should get it working again and see if it's easier to deal with now.
pjmlp 3y ago
Indeed and now AVX is what is left of it. The idea was good, the execution not so much.
RobotToaster 3y ago
Reminds me of the transputer https://en.wikipedia.org/wiki/Transputer https://en.wikipedia.org/wiki/Transputer

panick21_ 3y ago

One of the architects of Larrabee was very involved in RVV. He has some lots of good talks on Vector ISA stuff.

kjs3 3y ago

That was exactly what came to mind as well. "Big" RISC-V performance oriented cores for apps, gobs of "small" RISC-V cores ganged together for GPU. Larrabee didn't work out so good, though.

PaulHoule 3y ago
Skybox is closer to the old 1970s-1980s SIMD machines like ILLIAC and the Connection Machine or (I think) the current NVIDIA, it has two sets of added instructions, one has to do with managing multiple ‘wavefronts’ (like threads) that run the same instructions with the possibility of turning some off (predication, which was deliberately left out of RISC-V, would have been a help). The other instruction control fixed function units and do fused integer multiply-adds. I don’t see any talk about vector instructions.
pavlov 3y ago
In a similar vein, two decades ago there was the Sony/Toshiba/IBM Cell processor which ganged up a general-purpose PowerPC core with a cluster of lightweight co-processing PowerPC cores called SPEs: https://en.wikipedia.org/wiki/Cell_(processor) https://en.wikipedia.org/wiki/Cell_(processor) The idea was that Cell would also act as the GPU for the PlayStation 3, but performance wasn’t good enough when the chip was finally ready, so they ended up complementing it with an Nvidia GPU. The programming model was quite difficult. The SPE cores couldn’t directly access main memory. Instead they had small local SRAM buffers (256kB I believe) that the programmer would manually fill using explicit DMA commands either from other SPEs or from main memory. Orchestrating these memory operations for high performance must have been a chore, and when you do have the data, then you have to deal with the SPE having a different architecture with no branch prediction, etc. GPUs and CUDA turned out to be a much more palatable model for general-purpose compute.
- djmips 3y ago
  With some evolution, coders adapted to this model and found approaches that both worked well and even abstractions that made working with the SPEs both effective and not as much of a chore. In an interesting turn of events it turns out that if you could architect the SPEs to perform well the same basic approach helped unlock multi core performance on x86-64.
  - kjs3 3y ago
    Somewhere I have a CellBE PCI development board (from Mercury). I should get it working again and see if it's easier to deal with now.

pjmlp 3y ago

Indeed and now AVX is what is left of it. The idea was good, the execution not so much.

RobotToaster 3y ago

Reminds me of the transputer https://en.wikipedia.org/wiki/Transputer https://en.wikipedia.org/wiki/Transputer