5 ms·

> Then sprinkle down one 1uF 0402 per part for the small parts, or one per power pin for the big digital chips. Place these at the power pins, no exceptions Ho

> Then sprinkle down one 1uF 0402 per part for the small parts, or one per power pin for the big digital chips. Place these at the power pins, no exceptions How does this work for something like an FPGA ? Generally there will be several power rails (Vdd, Vio, Vpll, maybe Vusb, others) in an area far too tiny to put even 0102's let alone 0204's. Or maybe I'm just rubbish at placement :) I've been using double-sided placement underneath the FPGA as far as I can, but that also restricts the egress of the signals when you have as many power pins as an FPGA has... Any hints for power-pin-dense applications ? Enquiring minds want to know :)

15155 4y ago
How much do you want to spend? How many pins? How much unused I/O? What FPGA family? What ball pitch? What trace width? Blind and buried vias open up a whole world of space if you're willing to spend for them. You may just need to add more layers.
- spacedcowboy 4y ago
  I'm just a hobbyist, so regarding spending, the ever-popular "as little as possible" is close to my heart, given that each penny comes from my own pocket... I try to keep my BGAs limited to 256 pins if I can, but sometimes it will go higher - I'm looking at using an I.MXRT1176 for example, and that's 289 balls at 0.8mm pitch. I've also used Efinix FPGAs at 0.8mm pitch/256 balls. I've gone as low as 0.65mm pitch, but that is pushing the limits of where I want to be... It's fairly common to see 3.5mil as space/trace minimums nowadays (again in the cheap(er) Chinese PCB houses). That's still not quite enough to escape two traces between each outer ball on a 0.8mm grid - though reducing the solder pad and ignoring the warnings from the board-house has worked before :) I've never done blind/buried vias, they always seem to be a lot more expensive than the 6- or 8-layer boards I can get done for cheap at nextpcb or jlpcb. Maybe I ought to ask again... Things like FPGAs, DDR/HyperRAM ram, etc. used to be outside the province of hobbyists, but given the packaging for those high-frequency-capable pins, BGAs are ever-more common, and with them come the layout issues.
  - 15155 4y ago
    JLC will give you 5 pieces of 52mm x 52mm 8-layer boards with VIP, 3.5mil trace/3.5mil spacing for $2, no need to violate any constraints. +$20 to get much smaller vias/holes. Anecdote: I've routed a 900 pin 30x30 P=1mm/B=0.6mm FPGA with no issue on this. Use board-to-board connectors if needed to add more "layers." P=0.65mm is definitely going to make differential pairs difficult if not impossible at this trace width.
- InitialLastName 4y ago
  for BGA's, via-in-pad (plated over) makes decoupling caps almost too easy; do a VIPPO in each BGA pad; for the power pads, you can place the cap directly on the other side of the board. In many cases, the power pads are arranged next to corresponding ground pads and you can select a capacitor whose footprint exactly bridges those two vias.

15155 4y ago

How much do you want to spend? How many pins? How much unused I/O? What FPGA family? What ball pitch? What trace width? Blind and buried vias open up a whole world of space if you're willing to spend for them. You may just need to add more layers.

spacedcowboy 4y ago
I'm just a hobbyist, so regarding spending, the ever-popular "as little as possible" is close to my heart, given that each penny comes from my own pocket... I try to keep my BGAs limited to 256 pins if I can, but sometimes it will go higher - I'm looking at using an I.MXRT1176 for example, and that's 289 balls at 0.8mm pitch. I've also used Efinix FPGAs at 0.8mm pitch/256 balls. I've gone as low as 0.65mm pitch, but that is pushing the limits of where I want to be... It's fairly common to see 3.5mil as space/trace minimums nowadays (again in the cheap(er) Chinese PCB houses). That's still not quite enough to escape two traces between each outer ball on a 0.8mm grid - though reducing the solder pad and ignoring the warnings from the board-house has worked before :) I've never done blind/buried vias, they always seem to be a lot more expensive than the 6- or 8-layer boards I can get done for cheap at nextpcb or jlpcb. Maybe I ought to ask again... Things like FPGAs, DDR/HyperRAM ram, etc. used to be outside the province of hobbyists, but given the packaging for those high-frequency-capable pins, BGAs are ever-more common, and with them come the layout issues.
- 15155 4y ago
  JLC will give you 5 pieces of 52mm x 52mm 8-layer boards with VIP, 3.5mil trace/3.5mil spacing for $2, no need to violate any constraints. +$20 to get much smaller vias/holes. Anecdote: I've routed a 900 pin 30x30 P=1mm/B=0.6mm FPGA with no issue on this. Use board-to-board connectors if needed to add more "layers." P=0.65mm is definitely going to make differential pairs difficult if not impossible at this trace width.
InitialLastName 4y ago
for BGA's, via-in-pad (plated over) makes decoupling caps almost too easy; do a VIPPO in each BGA pad; for the power pads, you can place the cap directly on the other side of the board. In many cases, the power pads are arranged next to corresponding ground pads and you can select a capacitor whose footprint exactly bridges those two vias.