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RiscV & open chips seem to all be sticking to TileLink, an early intra & inter-chip interface. I keep wondering how long it will hold, or whether well see some
by rektide 4y ago
RiscV & open chips seem to all be sticking to TileLink, an early intra & inter-chip interface. I keep wondering how long it will hold, or whether well see some other interfaces come play.
I forgot about Interlaken. Might be useful, maybe?
- ajb 4y agoTilelink seems to be a memory interface, including cache coherency; Interlaken is a packet interface - each could be built on the other, but with less efficiency.
- convolvatron 4y agoidk if that is strictly true. coherency protocols can using an underlying framing/flit/error handling/flow control scheme just fine. treating coherency memory like a message protocol is possible, but would not just have constant performance problems, but scaling issues due to remote dictionary lookups. you could turn all that off with flags I guess.
- ajb 4y agoCache protocols usually have at least some optimisation for getting the accessed bytes first, which isn't normally present in a protocol designed to exchange packets. What I mean by that is that if your CPU reads byte 27 of a 32byte cache line, the cache is going to read 32 bytes from memory but it will start at byte 27 (or more likely bytes 24..27) so that it can unblock the CPU as fast as possible. I'm not actually sure if that makes its way down to the multicore coherency protocols - if the buses are sufficiently wide maybe they don't bother - but it's seems plausible.