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Intel’s first announced partnership to be a third party fab is to manufacture chips based on processes that were state of the art in 2013. TSMC doesn’t have mu

Intel’s first announced partnership to be a third party fab is to manufacture chips based on processes that were state of the art in 2013. TSMC doesn’t have much to fear in the near future. Edit: I see where the confusion lies. https://www.forbes.com/sites/patrickmoorhead/2022/08/10/intel-foundry-services-announces-mediatek-as-first-wafer-customer/?sh=721b210f464a https://www.forbes.com/sites/patrickmoorhead/2022/08/10/inte... This was announced two years ago. Intel hasn’t proven that it can be a third party manufacturer for anything close to cutting edge Intel announced they would be producing chips for MediaTek two years ago.

pedrocr 4y ago
Are you perhaps confusing 18A with 18nm? 18A is 1.8nm and is scheduled for the second half of 2024.
- sct202 4y ago
  They're referencing the first round of IFS which launched in 2013 and never really became much of anything but had a lot of announcements and fanfare at the time. Their foundry would have been the most advanced available foundry processes at the time had it launched as planned. From Feb 2013: https://www.reuters.com/article/us-altera-intel-manufacturing/intel-takes-big-step-in-chip-foundry-business-idUSBRE91O16G20130226 https://www.reuters.com/article/us-altera-intel-manufacturin...
  - scarface74 4y ago
    Actually I was referencing the MediaTek announcement https://www.forbes.com/sites/patrickmoorhead/2022/08/10/intel-foundry-services-announces-mediatek-as-first-wafer-customer/?sh=721b210f464a https://www.forbes.com/sites/patrickmoorhead/2022/08/10/inte...
Aromasin 4y ago
What on earth are you talking about? The article is discussing partnering with Arm using their 18A node. At 20A, Intel will be transitioning from its FinFET design over to a new type of transistor, known as a Gate-All-Around transistor, or GAAFET. In Intel’s case, the marketing name they are giving their version is RibbonFET. This is a technology that only started to come to a head in early 2020. The other arm of Intel’s 20A and onwards design is what the company is calling ‘PowerVia’. This is usually referred to as ‘backside power delivery’ in the industry. Although slightly older, we're still only talking about 2017 at the earliest. Intel has its 2nm node (called 20A, followed by 18A six months later) lined up for production to start in the first half of 2024, which compares to TSMC’s equivalent node (called N2) which is scheduled for the second half of 2025. 18A will be half a node denser than N2, while also being 12 months earlier to market. As to IFS as a concept, it's only recently been revamped in 2021 after a lackluster attempt in 2013 as you mentioned. So far they've announced partnerships with Arm, MediaTek, Qualcomm, AWS, and the DoD. That's a pretty heavy hitting pack, not including all of Tower Semiconductors customers. Intel wouldn't be building another 3 fabs if it wasn't serious this time about building capacity for other companies.
- fbn79 4y ago
  Interesting to know that "2nm" and "20A"(Armstrong) are just marketing names, they don't reflect physical sizes - see: https://en.wikipedia.org/wiki/2_nm_process#:~:text=The%20term%20%222,6%5D%5B7%5D https://en.wikipedia.org/wiki/2_nm_process#:~:text=The%20ter...
  - gibspaulding 4y ago
    My understanding is that hasn't been the case for a long time now. Wikipedia is saying the last node actually measured by transistor length was from 1994. https://en.m.wikipedia.org/wiki/Semiconductor_device_fabrication#Technology_node https://en.m.wikipedia.org/wiki/Semiconductor_device_fabrica...
  - smolder 4y ago
    Probably an autocorrect mishap, but in 20A the A is for angstrom.
- klelatti 4y ago
  > 18A will be half a node denser than N2, while also being 12 months earlier to market. It would be interesting to hear what the consensus view is on Intel actually being able to meet this timetable. Surely a strong degree of scepticism is warranted given their recent record.
  - chasil 4y ago
    A recent interview with Shang-Yi Chiang, former Vice President of R&D at TSMC (also held positions at TI, HP, and SMIC) had insightful commentary on the speed of bringing up a new node. "We all take two years to develop one generation, how come you guys can do it in one or one-and-a-half year?" And they asked if some of your customer transfer technology to you or what not? And I told him, "No," I told him that, "That's not true." I think he probably implied we steal technology from customer, the way he talk. And I say, "I'll tell you why." I said that, "When we develop one node, basically you have some learning cycles. First, you do some simulation. And you have some idea, then you run wafers to prove that. So, you run a group of wafers according to simulation and you have some splits. The wafer runs through the fab, they come out and you measure them, you analyze them, and you try to improve and you run this again. This again, you run. So, this is learning cycle." At that time, "It takes about six learning cycle, roughly, to complete one generation." Of course, you had some short loops and not just one. I said that, "My R&D wafer in the fab run much faster than yours, because my R&D engineer works three shifts and you only work one shift. So, your R&D wafer move eight hours a day, my work/move 24-hours a day. So, my wafers go three times faster, even if you are twice smarter than me, I still beat you up." <laughter> https://www.computerhistory.org/collections/catalog/102792671 https://www.computerhistory.org/collections/catalog/10279267...

pedrocr 4y ago

Are you perhaps confusing 18A with 18nm? 18A is 1.8nm and is scheduled for the second half of 2024.

sct202 4y ago
They're referencing the first round of IFS which launched in 2013 and never really became much of anything but had a lot of announcements and fanfare at the time. Their foundry would have been the most advanced available foundry processes at the time had it launched as planned. From Feb 2013: https://www.reuters.com/article/us-altera-intel-manufacturing/intel-takes-big-step-in-chip-foundry-business-idUSBRE91O16G20130226 https://www.reuters.com/article/us-altera-intel-manufacturin...
- scarface74 4y ago
  Actually I was referencing the MediaTek announcement https://www.forbes.com/sites/patrickmoorhead/2022/08/10/intel-foundry-services-announces-mediatek-as-first-wafer-customer/?sh=721b210f464a https://www.forbes.com/sites/patrickmoorhead/2022/08/10/inte...

Aromasin 4y ago

What on earth are you talking about? The article is discussing partnering with Arm using their 18A node. At 20A, Intel will be transitioning from its FinFET design over to a new type of transistor, known as a Gate-All-Around transistor, or GAAFET. In Intel’s case, the marketing name they are giving their version is RibbonFET. This is a technology that only started to come to a head in early 2020. The other arm of Intel’s 20A and onwards design is what the company is calling ‘PowerVia’. This is usually referred to as ‘backside power delivery’ in the industry. Although slightly older, we're still only talking about 2017 at the earliest. Intel has its 2nm node (called 20A, followed by 18A six months later) lined up for production to start in the first half of 2024, which compares to TSMC’s equivalent node (called N2) which is scheduled for the second half of 2025. 18A will be half a node denser than N2, while also being 12 months earlier to market. As to IFS as a concept, it's only recently been revamped in 2021 after a lackluster attempt in 2013 as you mentioned. So far they've announced partnerships with Arm, MediaTek, Qualcomm, AWS, and the DoD. That's a pretty heavy hitting pack, not including all of Tower Semiconductors customers. Intel wouldn't be building another 3 fabs if it wasn't serious this time about building capacity for other companies.

fbn79 4y ago
Interesting to know that "2nm" and "20A"(Armstrong) are just marketing names, they don't reflect physical sizes - see: https://en.wikipedia.org/wiki/2_nm_process#:~:text=The%20term%20%222,6%5D%5B7%5D https://en.wikipedia.org/wiki/2_nm_process#:~:text=The%20ter...
- gibspaulding 4y ago
  My understanding is that hasn't been the case for a long time now. Wikipedia is saying the last node actually measured by transistor length was from 1994. https://en.m.wikipedia.org/wiki/Semiconductor_device_fabrication#Technology_node https://en.m.wikipedia.org/wiki/Semiconductor_device_fabrica...
- smolder 4y ago
  Probably an autocorrect mishap, but in 20A the A is for angstrom.
klelatti 4y ago
> 18A will be half a node denser than N2, while also being 12 months earlier to market. It would be interesting to hear what the consensus view is on Intel actually being able to meet this timetable. Surely a strong degree of scepticism is warranted given their recent record.
- chasil 4y ago
  A recent interview with Shang-Yi Chiang, former Vice President of R&D at TSMC (also held positions at TI, HP, and SMIC) had insightful commentary on the speed of bringing up a new node. "We all take two years to develop one generation, how come you guys can do it in one or one-and-a-half year?" And they asked if some of your customer transfer technology to you or what not? And I told him, "No," I told him that, "That's not true." I think he probably implied we steal technology from customer, the way he talk. And I say, "I'll tell you why." I said that, "When we develop one node, basically you have some learning cycles. First, you do some simulation. And you have some idea, then you run wafers to prove that. So, you run a group of wafers according to simulation and you have some splits. The wafer runs through the fab, they come out and you measure them, you analyze them, and you try to improve and you run this again. This again, you run. So, this is learning cycle." At that time, "It takes about six learning cycle, roughly, to complete one generation." Of course, you had some short loops and not just one. I said that, "My R&D wafer in the fab run much faster than yours, because my R&D engineer works three shifts and you only work one shift. So, your R&D wafer move eight hours a day, my work/move 24-hours a day. So, my wafers go three times faster, even if you are twice smarter than me, I still beat you up." <laughter> https://www.computerhistory.org/collections/catalog/102792671 https://www.computerhistory.org/collections/catalog/10279267...