I only have one wish for PIOv2 in future chips: wire it up to the AHBlite bus as a target, behind a small cache, so i can make my own QSPI iface (or 8xSPI, or 1

I only have one wish for PIOv2 in future chips: wire it up to the AHBlite bus as a target, behind a small cache, so i can make my own QSPI iface (or 8xSPI, or 16xSPI, or SDRAM, etc)