> with the cpu needing to push W x H x BPP pixels Only if it needs to update the entire screen for every frame, which it probably doesn't. > Cortex M0 I belie

> with the cpu needing to push W x H x BPP pixels Only if it needs to update the entire screen for every frame, which it probably doesn't. > Cortex M0 I believe has 4 cycles for load and store, so even if you had a perfect parallel 16 bit bus where you could do 1 load + 1 store to send a pixel DMA can shovel data from RAM straight into the SPI peripheral with no CPU involvement beyond the initial setup (which is simple).