I've been in the semiconductor industry for 25 years. I do digital physical design using Cadence and Synopsys tools. I'm working in 5nm right now on huge SoC'

I've been in the semiconductor industry for 25 years. I do digital physical design using Cadence and Synopsys tools. I'm working in 5nm right now on huge SoC's I enjoy your videos and always look forward to watching them. I've actually learned quite a bit from you about fabs and lithography. I've never been in a fab and most of the theory I learned was in the 1990's. I meet DRC rules for stuff like double and quad pattering in 20/14/10nm but the industry is so segmented that I never see the actual challenges that lithography engineers run in to and how EUV has helped. Anyway, keep up the good work, everyone can always get better, but I would the ignore the overly negative comments