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Interposers. The start of "modern" chiplets was AMD's R9 Nano GPU, which I believe was the first to use HBM / stacked memory. Each stack has 1024 microbumps, a

Interposers. The start of "modern" chiplets was AMD's R9 Nano GPU, which I believe was the first to use HBM / stacked memory. Each stack has 1024 microbumps, and the GPU has 4 stacks, meaning 4096 bumps/pins connect the GPU with its RAM. EDIT: The pitch between these microbumps is 40 microns / 0.040 milimeters. This technology is "advanced packaging", the ability to provide thousands, or even tens-of-thousands, of bumps / effective pins to serve the signals going across our computers. ------------- Yeah, chiplets or even socket-to-socket communications, have existed for decades. But today we can take advantage of thousands, tens-of-thousands, or even hundreds-of-thousands of external "pins" that connect these components together. Here's a rundown on Intel's technology: https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros/4 https://www.anandtech.com/show/16823/intel-accelerated-offen... > Intel is also stating today that it will be using its second generation Foveros technology on the platform, implementing a bump pitch of 36 micron, effectively doubling the connection density over the first generation. 36 microns, or 36 um (micrometers) pitch density on Intel's advanced packaging technology. That's a lot of pins per mm^2! Now I don't know how these guys are lining up 0.036 milimeter bumps and reliably making connections. I kind of imagine a very tiny soldering iron, but I'm probably wrong. ------- In practice, AMD has led the way. Not only with "chiplets", but also off-die L3 cache (aka: x3d cache), adding 64MB of external SRAM to their chips through advanced packaging. So these thousands-of-microbumps are fast, reliable, and low-power enough to provide full-speed caches (something not quite possible with those earlier Pentiums you were talking about).

paulmd 4y ago
> Interposers. Interposers are just one way of packaging MCM designs. AMD's RX 7900 series doesn't use a silicon interposer, it's still an (early) MCM design (although of course it's only pulling out memory controllers and cache, not multi-GCD). And technically since it's already a fiberglass package, there's no reason you can't stick things right onto a PCB instead, it's just a matter of convenience for partners placing/routing one thing instead of 7 things. https://www.techpowerup.com/301071/amd-explains-the-economics-behind-chiplets-for-gpus https://www.techpowerup.com/301071/amd-explains-the-economic... Infinity Fanout integration is a different type of MCM integration with some of its own upsides (cost) and downsides (higher power, less bumpout). There's also bridges, and actual 3D stacks of multiple compute dies (or 2.5D with memory/etc) that don't use interposers at all. https://semiengineering.com/using-silicon-bridges-in-packages/ https://semiengineering.com/using-silicon-bridges-in-package... All of these are technically MCM - MCM is any sort of multi-chip package. MCM also really does include things like Core2Quad, Pentium-D, Crystalwell, Xenos, and various IBM modules in the 70s and 80s. The idea has been kicking around for a long time and "multi-chip module" refers to all of them collectively, not just interposer-based CPUs. https://en.wikipedia.org/wiki/Multi-chip_module https://en.wikipedia.org/wiki/Multi-chip_module And while yes, stacking and direct-bonding are great and lower power requirements a lot... there are still dies with stacking and no interposer! Ryzen x3d chips are a great example, v-cache is a MCM but there's no interposer there. And technically Ryzen itself (without v-cache) is also MCM too and still sees large benefits there too.

paulmd 4y ago

> Interposers. Interposers are just one way of packaging MCM designs. AMD's RX 7900 series doesn't use a silicon interposer, it's still an (early) MCM design (although of course it's only pulling out memory controllers and cache, not multi-GCD). And technically since it's already a fiberglass package, there's no reason you can't stick things right onto a PCB instead, it's just a matter of convenience for partners placing/routing one thing instead of 7 things. https://www.techpowerup.com/301071/amd-explains-the-economics-behind-chiplets-for-gpus https://www.techpowerup.com/301071/amd-explains-the-economic... Infinity Fanout integration is a different type of MCM integration with some of its own upsides (cost) and downsides (higher power, less bumpout). There's also bridges, and actual 3D stacks of multiple compute dies (or 2.5D with memory/etc) that don't use interposers at all. https://semiengineering.com/using-silicon-bridges-in-packages/ https://semiengineering.com/using-silicon-bridges-in-package... All of these are technically MCM - MCM is any sort of multi-chip package. MCM also really does include things like Core2Quad, Pentium-D, Crystalwell, Xenos, and various IBM modules in the 70s and 80s. The idea has been kicking around for a long time and "multi-chip module" refers to all of them collectively, not just interposer-based CPUs. https://en.wikipedia.org/wiki/Multi-chip_module https://en.wikipedia.org/wiki/Multi-chip_module And while yes, stacking and direct-bonding are great and lower power requirements a lot... there are still dies with stacking and no interposer! Ryzen x3d chips are a great example, v-cache is a MCM but there's no interposer there. And technically Ryzen itself (without v-cache) is also MCM too and still sees large benefits there too.