4 ms·
sadly Hu6502 sucked just as much. It had dedicated instructions, but cycle cost was ridiculous (17 + 6x) = ~160KB/s http://shu.emuunlim.com/download/pcedocs/pce
by rasz 4y ago
sadly Hu6502 sucked just as much. It had dedicated instructions, but cycle cost was ridiculous (17 + 6x) = ~160KB/s http://shu.emuunlim.com/download/pcedocs/pce_cpu.html http://shu.emuunlim.com/download/pcedocs/pce_cpu.html
Transfer Alternate Increment (TAI), Transfer Increment Alternate (TIA), Transfer Decrement Decrement (TDD), Transfer Increment Increment (TII)
For contrast 5 years older 80286 already did 'rep movsw' at afaik 2 cycles per byte. 6 years later Pentium did 'rep movsd' at 4 bytes per cycle. Nowadays Cannonlake can do 'rep movsb' full cachelines at a time at full cache/memory controller speed.
- rep_lodsb 4y agoWell the Z80 was worse. 21 cycles per byte! The reason is that instead of running a loop in microcode, it decremented PC by 2, then fetched the instruction again every time.
- deleted 4y ago[deleted]
- peterfirefly 4y agoIf you wanted to clear an area, LDIR/LDDR were slower than using a string of PUSH instructions. When moving data PUSH/POP were slightly slower than using LDIR/LDDR, though.