3 ms·
I think DRAM always worked this way. It's because the chips are physically organized into rows and columns, and the row must be selected first.
by rep_lodsb 4y ago
I think DRAM always worked this way. It's because the chips are physically organized into rows and columns, and the row must be selected first.
- kens 4y agoIt seems obvious to access DRAM that way, but multiplexing the address pins was a big innovation from Mostek for the 4K RAM chips, and they "bet the company" on this idea. Earlier DRAMs weren't multiplexed; Intel just kept adding address pins and ended up with a 22-pin 4K chip. Mostek multiplexed the pins so they could use a 16-pin package. The hard part is figuring out how to avoid slowing down the chip while you're waiting for both parts of the address. Mostek figured out how to implement the timing so the chip can access the row of memory cells while the column address is getting loaded. This required a bunch of clock generating circuitry on the chip, so it wasn't trivial. I discuss this in more detail in one of my blog posts: https://www.righto.com/2020/11/reverse-engineering-classic-mk4116-16.html#fn:multiplex https://www.righto.com/2020/11/reverse-engineering-classic-m...
- myself248 4y agoThat's great, and dovetails perfectly into a video I just watched on the topic, which I really enjoyed. It's a little flashy with the animations at first, but getting into the meat of things, they're used well: https://www.youtube.com/watch?v=7J7X7aZvMXQ https://www.youtube.com/watch?v=7J7X7aZvMXQ