3 ms·

Oops, thanks.

• userbinator 4y ago
  The 8086/88 does have an effective 4MB address space since it outputs the segment register in use during bus cycles, and I believe one of the official manuals did show that possibility, but I don't know of any systems that used such a configuration.
  • anyfoo 4y ago
    Today I learned. I in my mind briefly went through anything that would foil such a plan, but with no caches whatsoever... should indeed have worked, even if it's weird (and deeply incompatible with what PCs did, of course). The only thing that comes to mind is fetching vectors from the IDT. I guess it simply output CS in those cycles?