RISC is probably hard to do for a big desktop chip. AArch64 is more like regular than reduced instruction set computing. Its a very big complicated ISA but als

RISC is probably hard to do for a big desktop chip. AArch64 is more like regular than reduced instruction set computing. Its a very big complicated ISA but also not a complete mess like X86. RISC-V is reduced by these standards but requires a very real instruction count penalty. The compressed ISA performs it's job admirably, do keep in mind, but I think it remains to be seen if some of the aggressively simple/clean aspects of risc-v end up hurting it.