4 ms·

Very true, though there are some instruction sets with literally thousands - like the Intel x86-64. Give me RISC any day.

mhh__ 4y ago
RISC is probably hard to do for a big desktop chip. AArch64 is more like regular than reduced instruction set computing. Its a very big complicated ISA but also not a complete mess like X86. RISC-V is reduced by these standards but requires a very real instruction count penalty. The compressed ISA performs it's job admirably, do keep in mind, but I think it remains to be seen if some of the aggressively simple/clean aspects of risc-v end up hurting it.
deckard1 4y ago
x86 doesn't have thousands. That's overstating it by quite a bit. The assembler I wrote contains 1095 encodings. It's from ~2004 but 100% complete at the time, so sure new instructions have been added since. But those are encodings. SAL has like 8 encodings, SAR has 12, CMP has 14, etc. These encodings are just different ways to use the same opcode but with different source/target parameters (8/16/32-bit immediates or registers, etc.) Someone wrote a script that disassembled all the binaries on their Linux machine and counted the number of actual instructions used (mostly by gcc, of course). Only a tiny fraction of the total instructions were used: http://0x80.pl/notesen/2014-01-01-instruction-utilization.html http://0x80.pl/notesen/2014-01-01-instruction-utilization.ht... Just take the top 30 of that chart and learn those. The x86 contains a lot of instructions that no one needs to worry about. Things related to the ancient segment mode or x87 floating point, OS-privileged instructions (context switching, HLT/LIDT/etc.), AMD-only 3DNow, etc. The ISA is not the hard part anyway. Dealing with the ABI (System V on Linux) to interface with C/C++ code, the kernel syscall interface, position independent code/executable (PIC/PIE) are somewhat bigger concerns and are going to apply to RISC as well.
- xxs 4y ago
  >AMD-only 3DNow Modern AMD CPUs don't support it either, so it's entirely dead

mhh__ 4y ago

RISC is probably hard to do for a big desktop chip. AArch64 is more like regular than reduced instruction set computing. Its a very big complicated ISA but also not a complete mess like X86. RISC-V is reduced by these standards but requires a very real instruction count penalty. The compressed ISA performs it's job admirably, do keep in mind, but I think it remains to be seen if some of the aggressively simple/clean aspects of risc-v end up hurting it.

deckard1 4y ago

x86 doesn't have thousands. That's overstating it by quite a bit. The assembler I wrote contains 1095 encodings. It's from ~2004 but 100% complete at the time, so sure new instructions have been added since. But those are encodings. SAL has like 8 encodings, SAR has 12, CMP has 14, etc. These encodings are just different ways to use the same opcode but with different source/target parameters (8/16/32-bit immediates or registers, etc.) Someone wrote a script that disassembled all the binaries on their Linux machine and counted the number of actual instructions used (mostly by gcc, of course). Only a tiny fraction of the total instructions were used: http://0x80.pl/notesen/2014-01-01-instruction-utilization.html http://0x80.pl/notesen/2014-01-01-instruction-utilization.ht... Just take the top 30 of that chart and learn those. The x86 contains a lot of instructions that no one needs to worry about. Things related to the ancient segment mode or x87 floating point, OS-privileged instructions (context switching, HLT/LIDT/etc.), AMD-only 3DNow, etc. The ISA is not the hard part anyway. Dealing with the ABI (System V on Linux) to interface with C/C++ code, the kernel syscall interface, position independent code/executable (PIC/PIE) are somewhat bigger concerns and are going to apply to RISC as well.

xxs 4y ago
>AMD-only 3DNow Modern AMD CPUs don't support it either, so it's entirely dead