3 ms·

I don't dispute that legacy cruft is a problem, but I don't see how "not modern" (which still isn't defined) necessarily means legacy cruft. ARM or MIPS aren't

I don't dispute that legacy cruft is a problem, but I don't see how "not modern" (which still isn't defined) necessarily means legacy cruft. ARM or MIPS aren't especially recent in ISA terms, but I think most would agree each has less cruft in it than x86, for example.

brucehoult 4y ago
Less than x86, certainly. That's a low bar. MIPS has cruft in things such as architectural load and branch delay slots. Helped in the first, simple, implementation but just (worse than) useless baggage after that. Instructions that trap on overflow too. Helped on some programs on simple implementations, but on an OoO implementation just the mere existence vastly complicates the pipeline even if programs don't use them. With Arm, the bitmapped arbitrary set of registers load/store/push/pop is cruft that helped the first simple implementations (especially ones without icache). Same with the predication on every instruction. It uses a ton of instruction encoding space, doesn't get used much outside of conditional branches, and in modern implementations branch prediction is usually so good that you don't want to predicate instructions -- certainly not several in a row. Arm is deprecating IT* predication in Thumb2 now also. Also PC as a general register is harmful to modern implementations. ANY instruction with r15 as the destination can change control flow -- load, add, xor .. whatever. At least you can tell at instruction decode time, but it needs both opcode and dst register to tell. Aarch64 fixes most of the traditional Arm cruft (everything mentioned above) and is a pretty good ISA. The main faults are that it still has condition codes (no other high performance ISA designed after 1990 does), insistence on the purity of 4-byte instructions only (Thumb2 showed that the benefit is well worth the small cost), and just the simple fact that there is TOO MUCH of it and no subsets allowed, making it impractical for small CPUs e.g. microcontrollers.

brucehoult 4y ago

Less than x86, certainly. That's a low bar. MIPS has cruft in things such as architectural load and branch delay slots. Helped in the first, simple, implementation but just (worse than) useless baggage after that. Instructions that trap on overflow too. Helped on some programs on simple implementations, but on an OoO implementation just the mere existence vastly complicates the pipeline even if programs don't use them. With Arm, the bitmapped arbitrary set of registers load/store/push/pop is cruft that helped the first simple implementations (especially ones without icache). Same with the predication on every instruction. It uses a ton of instruction encoding space, doesn't get used much outside of conditional branches, and in modern implementations branch prediction is usually so good that you don't want to predicate instructions -- certainly not several in a row. Arm is deprecating IT* predication in Thumb2 now also. Also PC as a general register is harmful to modern implementations. ANY instruction with r15 as the destination can change control flow -- load, add, xor .. whatever. At least you can tell at instruction decode time, but it needs both opcode and dst register to tell. Aarch64 fixes most of the traditional Arm cruft (everything mentioned above) and is a pretty good ISA. The main faults are that it still has condition codes (no other high performance ISA designed after 1990 does), insistence on the purity of 4-byte instructions only (Thumb2 showed that the benefit is well worth the small cost), and just the simple fact that there is TOO MUCH of it and no subsets allowed, making it impractical for small CPUs e.g. microcontrollers.