It appears the OP article is just a rehash of SK Hynix press release [1], which is being republished by the usual suspects. Anandtech has a more jaundiced take

It appears the OP article is just a rehash of SK Hynix press release [1], which is being republished by the usual suspects. Anandtech has a more jaundiced take [2]. I don't think it's just buffering; registered memory is nothing new. It appears it's due more to latching; the MCR DIMMs are latching 128 bytes rather than the current 64 bytes, and is doubling how long (in bytes) a transfer burst lasts. This would reduce overhead for transfer setup. There may also be some bus clock boost. So, right now, appears to be lots of breathless PR regurgitation. [1] https://news.skhynix.com/sk-hynix-develops-mcr-dimm/ https://news.skhynix.com/sk-hynix-develops-mcr-dimm/ [2] https://www.anandtech.com/show/18683/sk-hynix-reveals-mcr-dimm-up-to-8gbps-bandwidth-for-hpc https://www.anandtech.com/show/18683/sk-hynix-reveals-mcr-di...