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Article has close to zero content. Total information: "Servers are running out of room for memory slots. DDR5 MCR will send 128 bytes at a time. Speed will inc

Article has close to zero content. Total information: "Servers are running out of room for memory slots. DDR5 MCR will send 128 bytes at a time. Speed will increase from current 4.8 Gbps to 8. Expected in 2024 or 2025." No descriptions of what's actually different. More lanes? Faster clock? More transitions per clock? How does it affect latency? How does it affect cache? Will going from 64 bytes to 128 cause problems with false cache line sharing? Etc...

Tuna-Fish 4y ago
What changes is that they add a new buffer chip on the dimm (the multiplexer), that all the memory chips talk to. This multiplexer can then connect to more memory chips than before without channel noise issues, allowing higher speeds on the interface. The downside is that minimum transfer unit for full bandwidth goes from 64B to 128B, while on x86 cache line width is 64B.
- mgsouth 4y ago
  It appears the OP article is just a rehash of SK Hynix press release [1], which is being republished by the usual suspects. Anandtech has a more jaundiced take [2]. I don't think it's just buffering; registered memory is nothing new. It appears it's due more to latching; the MCR DIMMs are latching 128 bytes rather than the current 64 bytes, and is doubling how long (in bytes) a transfer burst lasts. This would reduce overhead for transfer setup. There may also be some bus clock boost. So, right now, appears to be lots of breathless PR regurgitation. [1] https://news.skhynix.com/sk-hynix-develops-mcr-dimm/ https://news.skhynix.com/sk-hynix-develops-mcr-dimm/ [2] https://www.anandtech.com/show/18683/sk-hynix-reveals-mcr-dimm-up-to-8gbps-bandwidth-for-hpc https://www.anandtech.com/show/18683/sk-hynix-reveals-mcr-di...
- rektide 4y ago
  The transfer unit expanding is particularly hilarious because ddr4->ddr5 shrunk channel width from 64->32b and here we are immediately redoubling the transfer unit to add more memory. Good thing we shrank it, otherwise it'd be 256b!

Tuna-Fish 4y ago

What changes is that they add a new buffer chip on the dimm (the multiplexer), that all the memory chips talk to. This multiplexer can then connect to more memory chips than before without channel noise issues, allowing higher speeds on the interface. The downside is that minimum transfer unit for full bandwidth goes from 64B to 128B, while on x86 cache line width is 64B.

mgsouth 4y ago
It appears the OP article is just a rehash of SK Hynix press release [1], which is being republished by the usual suspects. Anandtech has a more jaundiced take [2]. I don't think it's just buffering; registered memory is nothing new. It appears it's due more to latching; the MCR DIMMs are latching 128 bytes rather than the current 64 bytes, and is doubling how long (in bytes) a transfer burst lasts. This would reduce overhead for transfer setup. There may also be some bus clock boost. So, right now, appears to be lots of breathless PR regurgitation. [1] https://news.skhynix.com/sk-hynix-develops-mcr-dimm/ https://news.skhynix.com/sk-hynix-develops-mcr-dimm/ [2] https://www.anandtech.com/show/18683/sk-hynix-reveals-mcr-dimm-up-to-8gbps-bandwidth-for-hpc https://www.anandtech.com/show/18683/sk-hynix-reveals-mcr-di...
rektide 4y ago
The transfer unit expanding is particularly hilarious because ddr4->ddr5 shrunk channel width from 64->32b and here we are immediately redoubling the transfer unit to add more memory. Good thing we shrank it, otherwise it'd be 256b!