10 ms·

iAPX432: Gordon Moore, Risk and Intel’s Super-CISC Failure

133 points by klelatti 4y ago

markhahn 4y ago
432 was a pretty interesting flop, but surely the ia64 has to rank up there. it would be interesting to try to chart some of the features that show up in various chips. for instance, 64k segments in both 432 and 286+, or VLIW in 860 and ia64.
- ghaff 4y ago
  One difference is that, according to the article, Intel actually learned quite a bit technically from the 432 even though it was a commercial flop. It's hard to see much of a silver lining in IA64/Itanium for either Intel or HP--or, indeed, for all the other companies that wasted resources on Itanium if only because they felt they had to cover their bases.
  - l1k 4y ago
    A lot of RISC CPU arches which were popular in the 1990's declined because their promulgators stopped investments and bet on switching to IA64 instead. Around the year 2000, VLIW was seen as the future and all the CISC and RISC architectures were considered obsolete. That strategic failure by competitors allowed x86 to grow market share at the high end, which benefited Intel more than the money lost on Itanium.
    - ghaff 4y ago
      It's more complicated than that. Sun didn't slow down on UltraSPARC or make an Itanium side bet. IBM did (and continues to) place their big hardware bet on Power--Itanium was mostly a cover your bases thing. I don't know what HP would have done--presumably either gone their own way with VLIW or kept PA-RISC going. Pretty much all the other RISC/Unix players had to go to a standard processor; some were already on x86. Intel mostly recovered from Itanium specifically but it didn't do them any favors.
      - panick21_ 4y ago
        Sun didn't slow down on UltraSPARC but they were just not very good at designing processors.
      - sliken 4y ago
        Actually, they did. Intel promised aggressive delivery schedule, performance ramp, and performance. The industry took it hook, line, and sinker. While AMD decided not to limit 64 bit to the high end and brought out x86-64. Sun did a port IA64 port of solaris, which is definitely an itanium side bet. HP was involved in the IA64 effort and definitely was planning on the replacement of pa-risc from day 1.
        davidgay 4y ago
        > HP was involved in the IA64 effort and definitely was planning on the replacement of pa-risc from day 1. As my memory remembers and https://en.wikipedia.org/wiki/Itanium https://en.wikipedia.org/wiki/Itanium agrees, Itanium originated at HP. So yes, a replacement for pa-risc from day 1, but even more so...
        rodgerd 4y ago
        Another way to look at the Itanic is that HP somehow conned Intel into betting the farm on building HP-PA3 for HP. Which is pretty impressive.
    - Dalewyn 4y ago
      >That strategic failure by competitors allowed x86 to grow market share at the high end, which benefited Intel more than the money lost on Itanium. In that sense, Itanium was a resounding success for Intel (and AMD).
      - panick21_ 4y ago
        Itanium was a success right until they actually made a chip. What they should have done is hype Itanium and then they day it came out they should have said yeah this was a joke, what we did is buy Alpha from Compaq and its literally just Alpha with x86 comparability mode. Then they would have dominated.
    - foobiekr 4y ago
      This isn't really true. IBM/Motorola need to own the failure of POWER and PowerPC and MIPS straight up died on the performance side. Sun continued with Ultrasparc. It wasn't that IA64 killed them, it's that they were getting shaky and IA64 appealed _because_ of that. Plus the lack of a 64bit x86.
      - panick21_ 4y ago
        Its simply economics Intel had the volume. Sun and SGI simply didn't have the economics to invest the same amount, and they were also not chip company, the both didn't invest enough in chip design or invested it wrongly. Sun spend an unbelievable amount of money on dumb ass processor projects. Towards the end of the 90s all of them realized their business model would not do well against Intel, so pretty much all of them were looking for an exit and IA64 hype basically killed most of them. Sun stuck it out with Sparc with mixed results. IBM POWER continues but in a thin slice of the market. Ironically there was a section of Digital and Intel who thought that Alpha should be the bases of 64 bit x86. That would have made Intel pretty dominate. Alpha (maybe a TSO version) with 32 bit x86 comparability mode.
        PAPPPmAc 4y ago
        Look closely at AMD designs (and staff) of the very late 90s and early 2000s and/or all modern x86 parts and see that ...more or less, that's what happened, just not with an Alpha mode. Dirk Meyer (Co-Architect of the DEC Alpha 21064 and 21264) lead the K7 (Athlon) project, and they run on a licensed EV6 bus borrowed from the Alpha. Jim Keller (Co-Architect of the DEC Alpha 21164 21264) lead the K8 (first gen x86-64) project, and there are a number of design decisions in the K8 evocative of the later Alpha designs. The vast majority of x86 parts since the (NexGen Nx686 which became) AMD K6 and Pentium Pro (P6) have been internal RISC-ish cores with decoders that ingest x86 instructions and chunk them up to be scheduled on an internal RISC architecture. It has turned out to sort of be a better-than-both-worlds thing almost by accident. A major part of what did in the VLIW-ish designs was that "You can't statically schedule dynamic behavior" and a major problem for the RISC designs was that exposing architectural innovations on a RISC requires you change the ISA and/or memory behavior in visible ways from generation to generation, interfering with compatability so... the RISC-behind-x86-decoder designs get to follow the state of the art changing whatever they need to behind the decoder without breaking compatibility AND get to have the decoder do the micro-scheduling dynamically.
  - _0w8t 4y ago
    Itanic was a flop due to AMD releasing 64bit CPU. And I still think Intel learned a lot from its failure if not from the technology but business-wise. Just stick to improving the existing architecture while keeping backward-compatibility.
    - markhahn 4y ago
      VLIW was really marooned in time: driven by overconfidence in the compiler (which had shown that you could actually expose pipeline hazards), and underestimates of the coming abundance of transistors (which make superscalar OoO really take off, along with giant onchip caches). well, and multicore to sop up even more available transistors.
      - panick21_ 4y ago
        The problem is that VLIW has already proven not to work in the 90s with lots of companies investing money in it but not making it a product. EPIC was basically VLIW++ with lots of added stuff that should overcome the issues with it, but not doing that successfully. I don't think they underestimated the amount of transistors, they just thought that EPIC would be a better way to use them. OoO had already proven itself in the 90s as well, so its not like this was unknown when they designed EPIC.
        kragen 4y ago
        otoh, for the previous 20 years, things like the 432 and lispms and burroughs large systems had been losing, in favor of architectures that pushed all the hard work onto compilers so it makes sense that in 01995 you'd look at ooo and vliw and extrapolate that vliw/epic was going to beat the crap out of ooo
        panick21_ 4y ago
        Granted it makes some amount of sense. But the issue is that with EPIC you still can address every part of the processor unless you want to continue to grow the instruction. So you end up having to do OoO anyway but you just made it much more complex and hard to reason about. I'm not a chip designer but is what I understood to be one of the issues. Also if this compiler stuff wasn't jet written, unlike with RISC where people at Standford showed successful compilation for RISC already before people even developed any high performance RISC chips. I don't want to claim I'm smarter then those people, clear all the people working on these VLIW processor were a lot smarter then me. But then again many smart people worked on Alpha and they didn't go the VLIW route.
twoodfin 4y ago
What’s most interesting to me about the i432 is the rich array of object types essentially embedded into its ISA. The JVM “knows” a little bit about virtual dispatch tables, monitors, arrays, but even that pales in comparison to the i432’s user-facing model of the CPU state. Is there anything comparable surviving today?
- yourapostasy 4y ago
  > Is there anything comparable surviving today? I'm not aware of such Super CISC instruction sets in popular use today, but I wonder with VM's and statistically-based AI proliferating now, whether we might revisit such architectures in the future. Could continuous VM-collected statistical data inform compiler and JIT compiler design to collapse expensive, common complex operations we can't identify patterns for with current methods into Super CISC instructions that substantially speed up patterns we didn't know previously existed, or are our current methods to analyze and implement compilers and JIT's good enough and what's mostly holding them back these days are other factors like memory and cache access speed and pipeline stalls?
- gumby 4y ago
  I don’t think so, except at the margins. I started out as a Lisp hacker on machines designed for it (PDP-10 and CADR, later D-machines) so I was very much in the camp you describe. They had hardware / microcode support for tagging, unboxing, fundamental Lisp opcodes, and for the Lispms specifically, things like a GC barrier and transporter support. When I looked at implementations like VAXLisp, the extra cycles needed to implement these things seemed like a burden to me. Of course those machines did lots of other things as well, and so were subject to a lot of evolutionary pressure the research machines were not subject to. The shocker that changed my mind was the idea of using the TLB to implement the write barrier. Yes, doing all that extra work cost cycles, but you were doing on a machine that had evolved lots of extra capabilities that could ameliorate some of the burden. Plus the underlying hardware just got faster faster (I.e. second derivative was higher). Meanwhile, the more dedicated architectures were burning valuable real estate on these features and couldn’t keep up elsewhere. You saw this in the article when the author wrote about gates that could have been used elsewhere. Finally, some decisions box you in — the 64kb object size limitation being an example in the 432. Sure, you can work around it, but then the support for these objects becomes a deadweight (part of the RISC argument). You see this also in the use of GPUs as huge parallel machines, even though the original programming abstraction was triangles. Going back to my first sentence about “at the margins”: optimize at the end. Apple famously added a “jvm” instruction — must have been the fruit of a lot of metering! Note that they didn’t have to do this for Objective-C: some extremely clever programming made dispatch cheap. Tagging/unboxing can be supported in a variety of (relatively) inexpensive ways by using ALU circuitry otherwise idle during address calculation OR (more likely these days) by implementing a couple of in demand ops, either way pretty cheap. Finally, we do have a return to and flourishing of separate, specialized functional units (image processors, “learning” units and such, like, say, the database hardware of old) but they aren’t generally fully programmable (even if they have processors embedded in them) but they key factor is that they don’t interfere (except via some DMA) with the core processing operations.
B1FF_PSUVM 4y ago
""" The key new features included: Ada : The architecture would be programmed using the Ada programming language, which at the time was seen as the ‘next big thing’ in languages. """ This was it - the next big thing. Missed and went down, but there's always the doubt if they were right too early ... Seems the performance just wasn't there: """ Gordon admitted that "to a significant extent," he was personally responsible. "It was a very aggressive shot at a new microprocessor, but we were so aggressive that the performance was way below par." """ It was kind of uncanny having it shouted from the rooftops one year, to dead silence about anything having ever happened a few years later.
- markhahn 4y ago
  Ada was the CISC of languages - high-concept the same way. And it lost to C, surely the RISC of languages. Never bet against low-tech.
  - lproven 4y ago
    > Ada was the CISC of languages - high-concept the same way. For a long time, many years, in the "programming language benchmarks game", Ada regularly and consistently came 2nd only to C in raw compiled-code execution speed. There is a huge but mostly unrecognised amount of hearsay, rumour and scuttlebutt in the computing industry. People hear something, believe it, and make choices based upon it, without checking or looking for evidence... as they do with medicine and so on, or there would be no "supplementary, complementary and alternative medicine". It doesn't work. It is a SCAM. People heard "Ada is big" and thought "big means slow" and avoided it. It was quite big in the 1980s, from what I can tell, but that was about 4-5 chip and software generations ago. (H/w: Caches, scalar, superscalar, multicore, 64-bit.) (S/w: 16-bit, no memory protection; 32-bit, ditto; 32-bit with memory protection; ubiquitous hypervisors; virtualised 64-bit with memory protection.) Compared to C++, Ada is a tiny lean fast sportscar of a language. > Never bet against low-tech. It isn't low-tech. It was in 1972 or something. Never bet against "worse is better" is more like it.
    - igouy 4y ago
nickdothutton 4y ago
I think the iAPX432 team went on to do the i960 (another interesting architecture that didn’t really find the success that was hoped-for) and then finally they went on to the PentiumPro where they found more success.
- convolvatron 4y ago
  it wasn't a total failure. the 860 and 960 were decent little engines that found a home in high performance computing and embedded applications that needed a little oomph. I worked on some 860 array products and certainly remember finding 960s in printers and other gear
  - trzy 4y ago
    Trivia: The i960 was used to power Sega's highly successful Model 2 arcade board, which truly ushered in the era of 3D gaming* (with Daytona USA), and was used in the F-22 Raptor until it was later replaced with other CPUs. * Certainly not the first 3D arcade hardware but arguably this along with Namco's MIPS-based System 22 (Ridge Racer, released a little before Daytona), was the inflection point that made 2D effectively obsolete.
  - speedbird 4y ago
    Worked on an i860 Stratus machine in the early 90s - provided a key part of our distributed infra due to its FT capabilities.
- panick21_ 4y ago
  Its really said the i960 didn't take off. Intel wasn't in Unix workstation market much and the high end was owned by Digital and IBM. Intel was working on i860, i960, Intel if they had added quicker, could have cooperated with a Unix workstation maker and potentially done really well. Sun was defiantly looking around for a chip partner at the time, but non of the American companies were interested so they went Japan. So the timing didn't really work out. A Sun Intel alliance would have been a scary prospect and beneficial for both companies.
jimmaswell 4y ago
If I recall correctly and shuttling instructions around fast enough is the main bottleneck right now, why do people want to return to RISC?
- t-3 4y ago
  Writing X86 assembly is painful, writing aarch64 or RISC-V assembly is easy and fun. That, and everything is fast nowadays. Even microcontrollers are hundreds of MHz with huge memories. There's very little pressure to increase high-end performance, a lot of pressure to make more software.
- yjftsjthsd-h 4y ago
  > If I recall correctly and shuttling instructions around fast enough is the main bottleneck right now, I don't think so? Aren't we still at the point in the cycle where moving data around is the bottleneck? Anyways, AIUI modern RISC does have tricks to make things more efficient if you really want, but it's not usually viewed as needed. > why do people want to return to RISC? What return? Nearly everything on the market is RISC; the one exception is x86, which is still RISC (ish) but with a CISC ISA stuck on top.
- DowsingSpoon 4y ago
  I think one of the main arguments in favor of RISC-V is the permissive licensing. A lot of the people moving to RISC-V are absolutely weighting this heavily in their decisions. The RISC-V folks would probably tell you that the compressed instruction set nets the same code density benefits you'd see on more complex ISAs. Myself, I haven't studied it enough to have a real opinion. RISC proponents tout its benefits for energy efficiency, which is a pretty important thing these days. Though, that might be up for debate. This paper states that "there is nothing fundamentally more energy efficient in one ISA class or the other. The ISA being RISC or CISC seems irrelevant." <https://research.cs.wisc.edu/vertical/papers/2013/hpca13-isa-power-struggles.pdf https://research.cs.wisc.edu/vertical/papers/2013/hpca13-isa...> Personally, I think the RISC vs CISC debate is just a little bit dated. The ideas behind RISC were new and exciting in the 80s. The equation had changed and there was a lot of room for innovation and improvement with sweeping changes to computer architecture. They were thinking about how instructions could be pipelined, how compilers would allocate registers, how profiling showed that seldom-used instructions can be deadweight that literally holds a system back. Then in the 90s, the equation changed again. Pentium Pro style superscalar architecture showed that you can do well with even a terrible ISA if you're able to throw enough transistors at it.
CalChris 4y ago
The ambitious 432 was also late, quite late. So Intel needed a simple stopgap product which was an iteration of the 8088, the 8086.
- wtallis 4y ago
  The 8088 (1979) was a low-cost (reduced bus width) follow-up to the 8086 (1978). You may be thinking of the 8080 (1974) or 8085 (1976).
  - CalChris 4y ago
    No, I meant the 8086. The iAPX 432 project was started in 1975 but wasn't released until 1981. The 432 was late, very late, and so Intel needed a stopgap product. That was the 8086, started in 1975 and released in 1979.
    - nkurz 4y ago
      I'm still not following. You seem to have said above that the 8086 was an iteration of the 8088, whereas Wikipedia claims that the 8088 is instead a variant of the 8086. It also says that the 8088 came out after the 8086. Can you restate and clarify your claim? A typo seems like the most likely explanation, but maybe I'm just misunderstanding.
      - CalChris 4y ago
        I'm only talking about the purpose of the 8086 as a stopgap for the very late 432. I shouldn't have mentioned the 8088.
djur 4y ago
There's something about this that gives the impression of an ISA that was developed in simulation without any real regard for hardware and then just tossed over the wall to be realized in silicon. I'm particularly baffled by instructions not being byte-aligned. Is there any successful processor that takes this "stream of bits" approach?
- Taniwha 4y ago
  It's actually not all that different from the Burroughs large systems architectures (B5000/B6700/A-series) which were initially released in the late 60s ... stack machines, similar descriptor based memory structures, tagged memory etc etc Burroughs instruction streams are on byte boundaries, and had variable length instructions starting with 1 byte, including long ones for making useful literals
  - pjmlp 4y ago
    And still being sold by Unisys to this day.
    - dfox 4y ago
      AFAIK what is sold today by Unisys are essentially preconfigured emulators running on what is otherwise normal Xeon servers.
      - pjmlp 4y ago
        Naturally Unisys ClearPath MCP isn't running the same hardware as Burrough Large Systems from 1961. They don't need emulators, as Burroughs was one of the first bytecode based OSes, but I am not sure how it looks in detail.
        skissane 4y ago
        > They don't need emulators, as Burroughs was one of the first bytecode based OSes, but I am not sure how it looks in detail. Do you have a source for that claim? I don't think that's true.
deleted 4y ago
[deleted]
VLM 4y ago
I've built stuff with 80s processors, like wire wrap and solder type of build, so I've read quite a few processor manuals/handbooks/datasheets over the years (decades...) After the failure of the 432 I saw a set of 432 databooks for sale cheap, probably at a hamfest or similar, the typical CPU of the day was a hundred page book but the 432 was an entire bookshelf. I know there's a marketing product message and we have to "respect" that, however... the impression I had from reading the actual engineering docs (well, glancing and skimming and having heard about it vs looking at the actual documentation) was marketing wanted to SELL an ada/object oriented chip, so they sold it that way, but the actual data sheet showed this was DESIGNED to be the IBM system/360 for the 80s microprocessor generation. Unimaginable list of features most applications would never, ever use. Literally every feature any assembly language programmer could ask for, and then more on top of that. It seemed too complicated to ever optimize and release a vers 2.0 that's binary compatible. You can imagine, then create, an 8008 version 2, or a 8080 version 2, or a 8086 version 2, or a 6800 version 2 in a logical engineering sense. The 432 was a one-and-done, an evolutionary dead end. Possibly the next one could be smaller process and run slightly faster or use less power. But it was a dead end.
- klelatti 4y ago
  > Literally every feature any assembly language programmer could ask for, and then more on top of that. I think that one of the key problems with the 432 was that they skipped talking to the assembly language programmers! The 432 omitted stuff that most assembly language would deem essential (eg registers where I think an assembly language expert would have immediately focused on performance impact) and I think assembly language programming of the 432 would not be fun at all. Agree 100% that upgrading it would have been a nightmare. I suspect that they simply didn’t have the bandwidth to think about v2.
- Tangurena2 4y ago
  I used to make similar computers: wire-wrapped things that I'd never do today - 8086, 80186 and twice 2900 bit slices. I was never able to purchase a set of 432 chips. No one had any for sale, or perhaps not for sale to me.

133 points by klelatti 4y ago

432 was a pretty interesting flop, but surely the ia64 has to rank up there. it would be interesting to try to chart some of the features that show up in various chips. for instance, 64k segments in both 432 and 286+, or VLIW in 860 and ia64.

ghaff 4y ago
One difference is that, according to the article, Intel actually learned quite a bit technically from the 432 even though it was a commercial flop. It's hard to see much of a silver lining in IA64/Itanium for either Intel or HP--or, indeed, for all the other companies that wasted resources on Itanium if only because they felt they had to cover their bases.
- l1k 4y ago
  A lot of RISC CPU arches which were popular in the 1990's declined because their promulgators stopped investments and bet on switching to IA64 instead. Around the year 2000, VLIW was seen as the future and all the CISC and RISC architectures were considered obsolete. That strategic failure by competitors allowed x86 to grow market share at the high end, which benefited Intel more than the money lost on Itanium.
  - ghaff 4y ago
    It's more complicated than that. Sun didn't slow down on UltraSPARC or make an Itanium side bet. IBM did (and continues to) place their big hardware bet on Power--Itanium was mostly a cover your bases thing. I don't know what HP would have done--presumably either gone their own way with VLIW or kept PA-RISC going. Pretty much all the other RISC/Unix players had to go to a standard processor; some were already on x86. Intel mostly recovered from Itanium specifically but it didn't do them any favors.
    - panick21_ 4y ago
      Sun didn't slow down on UltraSPARC but they were just not very good at designing processors.
    - sliken 4y ago
      Actually, they did. Intel promised aggressive delivery schedule, performance ramp, and performance. The industry took it hook, line, and sinker. While AMD decided not to limit 64 bit to the high end and brought out x86-64. Sun did a port IA64 port of solaris, which is definitely an itanium side bet. HP was involved in the IA64 effort and definitely was planning on the replacement of pa-risc from day 1.
      - davidgay 4y ago
        > HP was involved in the IA64 effort and definitely was planning on the replacement of pa-risc from day 1. As my memory remembers and https://en.wikipedia.org/wiki/Itanium https://en.wikipedia.org/wiki/Itanium agrees, Itanium originated at HP. So yes, a replacement for pa-risc from day 1, but even more so...
        rodgerd 4y ago
        Another way to look at the Itanic is that HP somehow conned Intel into betting the farm on building HP-PA3 for HP. Which is pretty impressive.
  - Dalewyn 4y ago
    >That strategic failure by competitors allowed x86 to grow market share at the high end, which benefited Intel more than the money lost on Itanium. In that sense, Itanium was a resounding success for Intel (and AMD).
    - panick21_ 4y ago
      Itanium was a success right until they actually made a chip. What they should have done is hype Itanium and then they day it came out they should have said yeah this was a joke, what we did is buy Alpha from Compaq and its literally just Alpha with x86 comparability mode. Then they would have dominated.
  - foobiekr 4y ago
    This isn't really true. IBM/Motorola need to own the failure of POWER and PowerPC and MIPS straight up died on the performance side. Sun continued with Ultrasparc. It wasn't that IA64 killed them, it's that they were getting shaky and IA64 appealed _because_ of that. Plus the lack of a 64bit x86.
    - panick21_ 4y ago
      Its simply economics Intel had the volume. Sun and SGI simply didn't have the economics to invest the same amount, and they were also not chip company, the both didn't invest enough in chip design or invested it wrongly. Sun spend an unbelievable amount of money on dumb ass processor projects. Towards the end of the 90s all of them realized their business model would not do well against Intel, so pretty much all of them were looking for an exit and IA64 hype basically killed most of them. Sun stuck it out with Sparc with mixed results. IBM POWER continues but in a thin slice of the market. Ironically there was a section of Digital and Intel who thought that Alpha should be the bases of 64 bit x86. That would have made Intel pretty dominate. Alpha (maybe a TSO version) with 32 bit x86 comparability mode.
      - PAPPPmAc 4y ago
        Look closely at AMD designs (and staff) of the very late 90s and early 2000s and/or all modern x86 parts and see that ...more or less, that's what happened, just not with an Alpha mode. Dirk Meyer (Co-Architect of the DEC Alpha 21064 and 21264) lead the K7 (Athlon) project, and they run on a licensed EV6 bus borrowed from the Alpha. Jim Keller (Co-Architect of the DEC Alpha 21164 21264) lead the K8 (first gen x86-64) project, and there are a number of design decisions in the K8 evocative of the later Alpha designs. The vast majority of x86 parts since the (NexGen Nx686 which became) AMD K6 and Pentium Pro (P6) have been internal RISC-ish cores with decoders that ingest x86 instructions and chunk them up to be scheduled on an internal RISC architecture. It has turned out to sort of be a better-than-both-worlds thing almost by accident. A major part of what did in the VLIW-ish designs was that "You can't statically schedule dynamic behavior" and a major problem for the RISC designs was that exposing architectural innovations on a RISC requires you change the ISA and/or memory behavior in visible ways from generation to generation, interfering with compatability so... the RISC-behind-x86-decoder designs get to follow the state of the art changing whatever they need to behind the decoder without breaking compatibility AND get to have the decoder do the micro-scheduling dynamically.
- _0w8t 4y ago
  Itanic was a flop due to AMD releasing 64bit CPU. And I still think Intel learned a lot from its failure if not from the technology but business-wise. Just stick to improving the existing architecture while keeping backward-compatibility.
  - markhahn 4y ago
    VLIW was really marooned in time: driven by overconfidence in the compiler (which had shown that you could actually expose pipeline hazards), and underestimates of the coming abundance of transistors (which make superscalar OoO really take off, along with giant onchip caches). well, and multicore to sop up even more available transistors.
    - panick21_ 4y ago
      The problem is that VLIW has already proven not to work in the 90s with lots of companies investing money in it but not making it a product. EPIC was basically VLIW++ with lots of added stuff that should overcome the issues with it, but not doing that successfully. I don't think they underestimated the amount of transistors, they just thought that EPIC would be a better way to use them. OoO had already proven itself in the 90s as well, so its not like this was unknown when they designed EPIC.
      - kragen 4y ago
        otoh, for the previous 20 years, things like the 432 and lispms and burroughs large systems had been losing, in favor of architectures that pushed all the hard work onto compilers so it makes sense that in 01995 you'd look at ooo and vliw and extrapolate that vliw/epic was going to beat the crap out of ooo
        panick21_ 4y ago
        Granted it makes some amount of sense. But the issue is that with EPIC you still can address every part of the processor unless you want to continue to grow the instruction. So you end up having to do OoO anyway but you just made it much more complex and hard to reason about. I'm not a chip designer but is what I understood to be one of the issues. Also if this compiler stuff wasn't jet written, unlike with RISC where people at Standford showed successful compilation for RISC already before people even developed any high performance RISC chips. I don't want to claim I'm smarter then those people, clear all the people working on these VLIW processor were a lot smarter then me. But then again many smart people worked on Alpha and they didn't go the VLIW route.

twoodfin 4y ago

What’s most interesting to me about the i432 is the rich array of object types essentially embedded into its ISA. The JVM “knows” a little bit about virtual dispatch tables, monitors, arrays, but even that pales in comparison to the i432’s user-facing model of the CPU state. Is there anything comparable surviving today?

yourapostasy 4y ago
> Is there anything comparable surviving today? I'm not aware of such Super CISC instruction sets in popular use today, but I wonder with VM's and statistically-based AI proliferating now, whether we might revisit such architectures in the future. Could continuous VM-collected statistical data inform compiler and JIT compiler design to collapse expensive, common complex operations we can't identify patterns for with current methods into Super CISC instructions that substantially speed up patterns we didn't know previously existed, or are our current methods to analyze and implement compilers and JIT's good enough and what's mostly holding them back these days are other factors like memory and cache access speed and pipeline stalls?
gumby 4y ago
I don’t think so, except at the margins. I started out as a Lisp hacker on machines designed for it (PDP-10 and CADR, later D-machines) so I was very much in the camp you describe. They had hardware / microcode support for tagging, unboxing, fundamental Lisp opcodes, and for the Lispms specifically, things like a GC barrier and transporter support. When I looked at implementations like VAXLisp, the extra cycles needed to implement these things seemed like a burden to me. Of course those machines did lots of other things as well, and so were subject to a lot of evolutionary pressure the research machines were not subject to. The shocker that changed my mind was the idea of using the TLB to implement the write barrier. Yes, doing all that extra work cost cycles, but you were doing on a machine that had evolved lots of extra capabilities that could ameliorate some of the burden. Plus the underlying hardware just got faster faster (I.e. second derivative was higher). Meanwhile, the more dedicated architectures were burning valuable real estate on these features and couldn’t keep up elsewhere. You saw this in the article when the author wrote about gates that could have been used elsewhere. Finally, some decisions box you in — the 64kb object size limitation being an example in the 432. Sure, you can work around it, but then the support for these objects becomes a deadweight (part of the RISC argument). You see this also in the use of GPUs as huge parallel machines, even though the original programming abstraction was triangles. Going back to my first sentence about “at the margins”: optimize at the end. Apple famously added a “jvm” instruction — must have been the fruit of a lot of metering! Note that they didn’t have to do this for Objective-C: some extremely clever programming made dispatch cheap. Tagging/unboxing can be supported in a variety of (relatively) inexpensive ways by using ALU circuitry otherwise idle during address calculation OR (more likely these days) by implementing a couple of in demand ops, either way pretty cheap. Finally, we do have a return to and flourishing of separate, specialized functional units (image processors, “learning” units and such, like, say, the database hardware of old) but they aren’t generally fully programmable (even if they have processors embedded in them) but they key factor is that they don’t interfere (except via some DMA) with the core processing operations.

B1FF_PSUVM 4y ago

""" The key new features included: Ada : The architecture would be programmed using the Ada programming language, which at the time was seen as the ‘next big thing’ in languages. """ This was it - the next big thing. Missed and went down, but there's always the doubt if they were right too early ... Seems the performance just wasn't there: """ Gordon admitted that "to a significant extent," he was personally responsible. "It was a very aggressive shot at a new microprocessor, but we were so aggressive that the performance was way below par." """ It was kind of uncanny having it shouted from the rooftops one year, to dead silence about anything having ever happened a few years later.

markhahn 4y ago
Ada was the CISC of languages - high-concept the same way. And it lost to C, surely the RISC of languages. Never bet against low-tech.
- lproven 4y ago
  > Ada was the CISC of languages - high-concept the same way. For a long time, many years, in the "programming language benchmarks game", Ada regularly and consistently came 2nd only to C in raw compiled-code execution speed. There is a huge but mostly unrecognised amount of hearsay, rumour and scuttlebutt in the computing industry. People hear something, believe it, and make choices based upon it, without checking or looking for evidence... as they do with medicine and so on, or there would be no "supplementary, complementary and alternative medicine". It doesn't work. It is a SCAM. People heard "Ada is big" and thought "big means slow" and avoided it. It was quite big in the 1980s, from what I can tell, but that was about 4-5 chip and software generations ago. (H/w: Caches, scalar, superscalar, multicore, 64-bit.) (S/w: 16-bit, no memory protection; 32-bit, ditto; 32-bit with memory protection; ubiquitous hypervisors; virtualised 64-bit with memory protection.) Compared to C++, Ada is a tiny lean fast sportscar of a language. > Never bet against low-tech. It isn't low-tech. It was in 1972 or something. Never bet against "worse is better" is more like it.
  - igouy 4y ago

nickdothutton 4y ago

I think the iAPX432 team went on to do the i960 (another interesting architecture that didn’t really find the success that was hoped-for) and then finally they went on to the PentiumPro where they found more success.

convolvatron 4y ago
it wasn't a total failure. the 860 and 960 were decent little engines that found a home in high performance computing and embedded applications that needed a little oomph. I worked on some 860 array products and certainly remember finding 960s in printers and other gear
- trzy 4y ago
  Trivia: The i960 was used to power Sega's highly successful Model 2 arcade board, which truly ushered in the era of 3D gaming* (with Daytona USA), and was used in the F-22 Raptor until it was later replaced with other CPUs. * Certainly not the first 3D arcade hardware but arguably this along with Namco's MIPS-based System 22 (Ridge Racer, released a little before Daytona), was the inflection point that made 2D effectively obsolete.
- speedbird 4y ago
  Worked on an i860 Stratus machine in the early 90s - provided a key part of our distributed infra due to its FT capabilities.
panick21_ 4y ago
Its really said the i960 didn't take off. Intel wasn't in Unix workstation market much and the high end was owned by Digital and IBM. Intel was working on i860, i960, Intel if they had added quicker, could have cooperated with a Unix workstation maker and potentially done really well. Sun was defiantly looking around for a chip partner at the time, but non of the American companies were interested so they went Japan. So the timing didn't really work out. A Sun Intel alliance would have been a scary prospect and beneficial for both companies.

jimmaswell 4y ago

If I recall correctly and shuttling instructions around fast enough is the main bottleneck right now, why do people want to return to RISC?

t-3 4y ago
Writing X86 assembly is painful, writing aarch64 or RISC-V assembly is easy and fun. That, and everything is fast nowadays. Even microcontrollers are hundreds of MHz with huge memories. There's very little pressure to increase high-end performance, a lot of pressure to make more software.
yjftsjthsd-h 4y ago
> If I recall correctly and shuttling instructions around fast enough is the main bottleneck right now, I don't think so? Aren't we still at the point in the cycle where moving data around is the bottleneck? Anyways, AIUI modern RISC does have tricks to make things more efficient if you really want, but it's not usually viewed as needed. > why do people want to return to RISC? What return? Nearly everything on the market is RISC; the one exception is x86, which is still RISC (ish) but with a CISC ISA stuck on top.
DowsingSpoon 4y ago
I think one of the main arguments in favor of RISC-V is the permissive licensing. A lot of the people moving to RISC-V are absolutely weighting this heavily in their decisions. The RISC-V folks would probably tell you that the compressed instruction set nets the same code density benefits you'd see on more complex ISAs. Myself, I haven't studied it enough to have a real opinion. RISC proponents tout its benefits for energy efficiency, which is a pretty important thing these days. Though, that might be up for debate. This paper states that "there is nothing fundamentally more energy efficient in one ISA class or the other. The ISA being RISC or CISC seems irrelevant." <https://research.cs.wisc.edu/vertical/papers/2013/hpca13-isa-power-struggles.pdf https://research.cs.wisc.edu/vertical/papers/2013/hpca13-isa...> Personally, I think the RISC vs CISC debate is just a little bit dated. The ideas behind RISC were new and exciting in the 80s. The equation had changed and there was a lot of room for innovation and improvement with sweeping changes to computer architecture. They were thinking about how instructions could be pipelined, how compilers would allocate registers, how profiling showed that seldom-used instructions can be deadweight that literally holds a system back. Then in the 90s, the equation changed again. Pentium Pro style superscalar architecture showed that you can do well with even a terrible ISA if you're able to throw enough transistors at it.

CalChris 4y ago

The ambitious 432 was also late, quite late. So Intel needed a simple stopgap product which was an iteration of the 8088, the 8086.

wtallis 4y ago
The 8088 (1979) was a low-cost (reduced bus width) follow-up to the 8086 (1978). You may be thinking of the 8080 (1974) or 8085 (1976).
- CalChris 4y ago
  No, I meant the 8086. The iAPX 432 project was started in 1975 but wasn't released until 1981. The 432 was late, very late, and so Intel needed a stopgap product. That was the 8086, started in 1975 and released in 1979.
  - nkurz 4y ago
    I'm still not following. You seem to have said above that the 8086 was an iteration of the 8088, whereas Wikipedia claims that the 8088 is instead a variant of the 8086. It also says that the 8088 came out after the 8086. Can you restate and clarify your claim? A typo seems like the most likely explanation, but maybe I'm just misunderstanding.
    - CalChris 4y ago
      I'm only talking about the purpose of the 8086 as a stopgap for the very late 432. I shouldn't have mentioned the 8088.

djur 4y ago

There's something about this that gives the impression of an ISA that was developed in simulation without any real regard for hardware and then just tossed over the wall to be realized in silicon. I'm particularly baffled by instructions not being byte-aligned. Is there any successful processor that takes this "stream of bits" approach?

Taniwha 4y ago
It's actually not all that different from the Burroughs large systems architectures (B5000/B6700/A-series) which were initially released in the late 60s ... stack machines, similar descriptor based memory structures, tagged memory etc etc Burroughs instruction streams are on byte boundaries, and had variable length instructions starting with 1 byte, including long ones for making useful literals
- pjmlp 4y ago
  And still being sold by Unisys to this day.
  - dfox 4y ago
    AFAIK what is sold today by Unisys are essentially preconfigured emulators running on what is otherwise normal Xeon servers.
    - pjmlp 4y ago
      Naturally Unisys ClearPath MCP isn't running the same hardware as Burrough Large Systems from 1961. They don't need emulators, as Burroughs was one of the first bytecode based OSes, but I am not sure how it looks in detail.
      - skissane 4y ago
        > They don't need emulators, as Burroughs was one of the first bytecode based OSes, but I am not sure how it looks in detail. Do you have a source for that claim? I don't think that's true.

deleted 4y ago

[deleted]

VLM 4y ago

I've built stuff with 80s processors, like wire wrap and solder type of build, so I've read quite a few processor manuals/handbooks/datasheets over the years (decades...) After the failure of the 432 I saw a set of 432 databooks for sale cheap, probably at a hamfest or similar, the typical CPU of the day was a hundred page book but the 432 was an entire bookshelf. I know there's a marketing product message and we have to "respect" that, however... the impression I had from reading the actual engineering docs (well, glancing and skimming and having heard about it vs looking at the actual documentation) was marketing wanted to SELL an ada/object oriented chip, so they sold it that way, but the actual data sheet showed this was DESIGNED to be the IBM system/360 for the 80s microprocessor generation. Unimaginable list of features most applications would never, ever use. Literally every feature any assembly language programmer could ask for, and then more on top of that. It seemed too complicated to ever optimize and release a vers 2.0 that's binary compatible. You can imagine, then create, an 8008 version 2, or a 8080 version 2, or a 8086 version 2, or a 6800 version 2 in a logical engineering sense. The 432 was a one-and-done, an evolutionary dead end. Possibly the next one could be smaller process and run slightly faster or use less power. But it was a dead end.

klelatti 4y ago
> Literally every feature any assembly language programmer could ask for, and then more on top of that. I think that one of the key problems with the 432 was that they skipped talking to the assembly language programmers! The 432 omitted stuff that most assembly language would deem essential (eg registers where I think an assembly language expert would have immediately focused on performance impact) and I think assembly language programming of the 432 would not be fun at all. Agree 100% that upgrading it would have been a nightmare. I suspect that they simply didn’t have the bandwidth to think about v2.
Tangurena2 4y ago
I used to make similar computers: wire-wrapped things that I'd never do today - 8086, 80186 and twice 2900 bit slices. I was never able to purchase a set of 432 chips. No one had any for sale, or perhaps not for sale to me.