3 ms·
I submitted 2 CPUs to TT2 and a PDP8 (12 bits) to the current TT3. The major limitations are the relatively small number of gates, and the external interface (
by Taniwha 4y ago
I submitted 2 CPUs to TT2 and a PDP8 (12 bits) to the current TT3.
The major limitations are the relatively small number of gates, and the external interface (8 inputs including clock/reset, and 8 outputs) - and the external multiplexor which essentially limits clock frequencies to tens of kilohertz.
TT4 and later will have a redesigned pin interface and likely have roughly twice as many external pins and far faster clocks - a lot of my designs are gates spent talking over that tiny interface
- Taniwha 4y agoI'll also note that all Tiny Tapeout projects are hosted on github and you can browse through them if you want to see how they're done
- userbinator 4y agoand the external interface (8 inputs including clock/reset, and 8 outputs) That's around the same amount of I/O as an Intel 4004.
- Gordonjcp 4y ago> and a PDP8 (12 bits) Interested. Is this going to be something like the Intersil 6120?
- Taniwha 4y agoProbably a bit smaller - and doesn't have a multiplier/divider (it does have the minimal MQ register instructions), and it has a minimal IO interface In some sense it's a toy because the TT internal clock is so slow and it needs to run 5 clocks/memory cycle because of the tiny bus interface - ideally in say TT 4 with ~16 bits each way in the IO bus we could actually make something that could outperform an original PDP8 You can find it here: https://github.com/MoonbaseOtago/tt03-pdp8/blob/main/src/cpu.v https://github.com/MoonbaseOtago/tt03-pdp8/blob/main/src/cpu...