It is an interesting problem, and it has of course had some analysis done to it over the years. I particularly like Analog Device's take[0]. Note that the stan

It is an interesting problem, and it has of course had some analysis done to it over the years. I particularly like Analog Device's take[0]. Note that the standard UART byte (8N1) has 10 bits (1 start + 8 data + 1 stop). Use of parity is not at all common. To accumulate 50% you need to be 5% off per-bit. This is the naive approach, with a single sample in the middle of the bit. Super-sampling and clever clock recovery tricks can get you much better tolerance. An example such as the +4.58/-4.54 on the whole message even older atmega8[1] achieve. They are not even chips designed to be dedicated to UART. This is pretty good, while still working bit by bit. A strong implementation can go considerably further by super-sampling the whole message, and sampling past the expected end. By super sampling the whole message and an extra bit, you can get to that 10%, or tolerance of clock being off by a whole bit. ch340 and variants likely do not supersample at all, in addition to using a poor (not xtal oscillator) clock source, and that's why they do that poorly. 0. https://archive.is/8wEkZ https://archive.is/8wEkZ 1. (p144) https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-2486-8-bit-AVR-microcontroller-ATmega8_L_datasheet.pdf https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-2486-...